parent
5a236dd35d
commit
e36838ad8e
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@ -1645,7 +1645,8 @@ class TristateVisitor final : public TristateBaseVisitor {
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AstPin* const enpinp
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= new AstPin{nodep->fileline(), nodep->pinNum(),
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enModVarp->name(), // should be {var}"__en"
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new AstVarRef{nodep->fileline(), enVarp, VAccess::WRITE}};
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new AstVarRef{nodep->fileline(), enVarp,
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inDeclProcessing ? VAccess::READ : VAccess::WRITE}};
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enpinp->modVarp(enModVarp);
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UINFO(9, " newpin " << enpinp);
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enpinp->user2Or(U2_BOTH); // don't iterate the pin later
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@ -0,0 +1,19 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.top_filename = "t/t_altera_lpm.v"
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module = re.sub(r'.*t_altera_', '', test.name)
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module = re.sub(r'_noinl', '', module)
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test.compile(verilator_flags2=["--top-module", module, "-fno-inline"])
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test.passes()
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