Fix --debug-inputs for .vlt files

src/V3ParseImp.cpp

@@ -276,6 +276,7 @@ size_t V3ParseImp::ppInputToLex(char* buf, size_t max_size) {
 void V3ParseImp::preprocDumps(std::ostream& os, bool forInputs) {
     bool noblanks = forInputs || (v3Global.opt.preprocOnly() && v3Global.opt.preprocNoLine());
     bool nolines = forInputs;
+    bool anyNonVerilog = false;
     for (auto& buf : m_ppBuffers) {
         if (noblanks) {
             bool blank = true;
@@ -287,9 +288,12 @@ void V3ParseImp::preprocDumps(std::ostream& os, bool forInputs) {
             }
             if (blank) continue;
             if (nolines && buf.rfind("`line ", 0) == 0) continue;
+            // Ignores comments, but over-positive match search should be ok
+            if (forInputs && buf.rfind("`verilator_config", 0) == 0) anyNonVerilog = true;
         }
         os << buf;
     }
+    if (forInputs && anyNonVerilog) os << "\n`verilog\n";
 }
 
 void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool inLibrary,

src/verilog.l

@@ -1172,6 +1172,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
                                                   FL_BRK; }
 
   /* Verilator */
+  /* See also V3ParseImp::preprocDumps() */
   "`systemc_ctor"                       { FL_FWD; BEGIN SYSCCTOR; FL_BRK; }
   "`systemc_dtor"                       { FL_FWD; BEGIN SYSCDTOR; FL_BRK; }
   "`systemc_header"                     { FL_FWD; BEGIN SYSCHDR; FL_BRK; }

test_regress/t/t_debug_inputs.py

@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('vlt')
 
-test.lint(v_flags=["--dump-inputs -Wno-MULTITOP t/t_debug_inputs_b.v"])
+test.lint(v_flags=["--dump-inputs -Wno-MULTITOP t/t_debug_inputs.vlt t/t_debug_inputs_b.v"])
 
 test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs;')
 test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_a;')

test_regress/t/t_debug_inputs.vlt

@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference
+// as the select expression
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+// Nothing needed, just testing `verilator_config handling without
+// terminating in a `verilog