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Verilog format

This commit is contained in:
Veripool API Bot 2026-02-05 17:45:24 -05:00 committed by Wilson Snyder
parent c83ae4a3ca
commit b82f6beffb
20 changed files with 785 additions and 517 deletions
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2
docs/spelling.txt
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@ -478,7 +478,9 @@ Tarik
Tariq
Tejada
Tengstrand
Tenstorrent
Terpstra
Testorrent
Thiede
Thierry
Thyer

4
test_regress/t/t_foreach_nested.v
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@ -4,9 +4,7 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
typedef struct {
int x[9][9];
} Foo;
typedef struct {int x[9][9];} Foo;
class Bar;
Foo foo;

54
test_regress/t/t_fourstate_assign.v
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@ -5,37 +5,37 @@
// SPDX-License-Identifier: CC0-1.0
module t;
// 2-state arrays - assignment should work
bit [7:0] arr_2state_a [3:0];
bit [7:0] arr_2state_b [3:0];
// 2-state arrays - assignment should work
bit [7:0] arr_2state_a[3:0];
bit [7:0] arr_2state_b[3:0];
// 4-state arrays - assignment should work
logic [7:0] arr_4state_a [3:0];
logic [7:0] arr_4state_b [3:0];
// 4-state arrays - assignment should work
logic [7:0] arr_4state_a[3:0];
logic [7:0] arr_4state_b[3:0];
initial begin
// Initialize
arr_2state_a[0] = 8'h10;
arr_2state_a[1] = 8'h20;
arr_2state_a[2] = 8'h30;
arr_2state_a[3] = 8'h40;
initial begin
// Initialize
arr_2state_a[0] = 8'h10;
arr_2state_a[1] = 8'h20;
arr_2state_a[2] = 8'h30;
arr_2state_a[3] = 8'h40;
arr_4state_a[0] = 8'hA0;
arr_4state_a[1] = 8'hB0;
arr_4state_a[2] = 8'hC0;
arr_4state_a[3] = 8'hD0;
arr_4state_a[0] = 8'hA0;
arr_4state_a[1] = 8'hB0;
arr_4state_a[2] = 8'hC0;
arr_4state_a[3] = 8'hD0;
// Valid assignments: same state types
arr_2state_b = arr_2state_a; // 2-state to 2-state: OK
arr_4state_b = arr_4state_a; // 4-state to 4-state: OK
// Valid assignments: same state types
arr_2state_b = arr_2state_a; // 2-state to 2-state: OK
arr_4state_b = arr_4state_a; // 4-state to 4-state: OK
// Verify
if (arr_2state_b[0] !== 8'h10) $stop;
if (arr_2state_b[3] !== 8'h40) $stop;
if (arr_4state_b[0] !== 8'hA0) $stop;
if (arr_4state_b[3] !== 8'hD0) $stop;
// Verify
if (arr_2state_b[0] !== 8'h10) $stop;
if (arr_2state_b[3] !== 8'h40) $stop;
if (arr_4state_b[0] !== 8'hA0) $stop;
if (arr_4state_b[3] !== 8'hD0) $stop;
$write("*-* All Coverage *-*\n");
$finish;
end
$write("*-* All Coverage *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_fourstate_assign_bad.out
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@ -1,8 +1,8 @@
%Error: t/t_fourstate_assign_bad.v:23:18: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6)
%Error: t/t_fourstate_assign_bad.v:23:16: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6)
: ... note: In instance 't'
: ... LHS type: 'bit[7:0]$[3:0]' (2-state)
: ... RHS type: 'logic[7:0]$[3:0]' (4-state)
23 | arr_2state = arr_4state;
| ^
23 | arr_2state = arr_4state;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

30
test_regress/t/t_fourstate_assign_bad.v
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@ -6,22 +6,22 @@
// SPDX-License-Identifier: CC0-1.0
module t;
// IEEE 6.22.2: Packed arrays are equivalent if they contain the same number
// of total bits, are either all 2-state or all 4-state, and are either all
// signed or all unsigned.
// IEEE 6.22.2: Packed arrays are equivalent if they contain the same number
// of total bits, are either all 2-state or all 4-state, and are either all
// signed or all unsigned.
// 2-state array
bit [7:0] arr_2state [3:0];
// 2-state array
bit [7:0] arr_2state[3:0];
// 4-state array (should not be assignment compatible for unpacked arrays)
logic [7:0] arr_4state [3:0];
// 4-state array (should not be assignment compatible for unpacked arrays)
logic [7:0] arr_4state[3:0];
initial begin
// Per IEEE 7.6: For unpacked arrays to be assignment compatible,
// the element types shall be equivalent.
// bit[7:0] and logic[7:0] are NOT equivalent (one is 2-state, one is 4-state)
arr_2state = arr_4state;
$write("*-* All Coverage *-*\n");
$stop;
end
initial begin
// Per IEEE 7.6: For unpacked arrays to be assignment compatible,
// the element types shall be equivalent.
// bit[7:0] and logic[7:0] are NOT equivalent (one is 2-state, one is 4-state)
arr_2state = arr_4state;
$write("*-* All Coverage *-*\n");
$stop;
end
endmodule

8
test_regress/t/t_gantt_numa_default_threads.cpp
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@ -1,10 +1,10 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
//
// Copyright 2026 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// This program is free software; you can redistribute it and/or modify it
// under the terms of either the GNU Lesser General Public License Version 3
// or the Perl Artistic License Version 2.0.
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************

8
test_regress/t/t_gantt_numa_default_threads.py
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@ -1,10 +1,10 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2026 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import os

16
test_regress/t/t_iface_param_class_typedef.v
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@ -12,21 +12,25 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
class flux_st #(parameter int WIDTH=32);
typedef struct packed { logic [WIDTH-1:0] data; } pld_t;
class flux_st #(
parameter int WIDTH = 32
);
typedef struct packed {logic [WIDTH-1:0] data;} pld_t;
endclass
interface flux_if #(parameter type PLD_T = logic);
interface flux_if #(
parameter type PLD_T = logic
);
logic rdy;
logic vld;
PLD_T pld;
modport drive (input rdy, output vld, output pld);
modport sink (output rdy, input vld, input pld);
modport drive(input rdy, output vld, output pld);
modport sink(output rdy, input vld, input pld);
endinterface
module t;
// Test using parameterized class typedef as interface type parameter
flux_if #(flux_st#(64)::pld_t) w_flux_st ();
flux_if #(flux_st #(64)::pld_t) w_flux_st ();
initial begin
`checkd($bits(w_flux_st.pld), 64);

22
test_regress/t/t_inline_varxref_inlineddots.v
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@ -4,22 +4,36 @@
// SPDX-FileCopyrightText: 2026 Leela Pakanati
// SPDX-License-Identifier: CC0-1.0
module src #(parameter [3:0] VAL = 4'h0) (output logic [3:0] val);
module src #(
parameter [3:0] VAL = 4'h0
) (
output logic [3:0] val
);
/*verilator no_inline_module*/
assign val = VAL;
endmodule
module inner (input logic [3:0] in, output logic [3:0] out);
module inner (
input logic [3:0] in,
output logic [3:0] out
);
/*verilator inline_module*/
assign out = in;
endmodule
module outer #(parameter [3:0] VAL = 4'h0) (output logic [3:0] out);
module outer #(
parameter [3:0] VAL = 4'h0
) (
output logic [3:0] out
);
/*verilator inline_module*/
logic [3:0] s_val;
src #(.VAL(VAL)) s (.val(s_val));
// Use hierarchical ref s.val (not s_val) to test inlinedDots propagation
inner u (.in(s.val), .out(out));
inner u (
.in(s.val),
.out(out)
);
endmodule
module t;

8
test_regress/t/t_inst_port_complex_unsup.py
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@ -1,10 +1,10 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2026 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap

4
test_regress/t/t_inst_port_complex_unsup.v
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@ -1,7 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2015 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// No simulator supporting this was found

331
test_regress/t/t_interface_nested_port.v
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@ -16,229 +16,304 @@
// L4(W=4) -> L3(W=8) -> L2A(W=16) -> L1(W=32) -> L0A(W=16), L0B(W=8)
// -> L2B(W=8) -> L1(W=16) -> L0A(W=16), L0B(W=8)
interface l0_if #(parameter int W = 8);
interface l0_if #(
parameter int W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
endinterface
interface l1_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l1_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l0_if #(L0A_W) l0a(); // passthrough
l0_if l0b(); // default
l0_if #(L0A_W) l0a (); // passthrough
l0_if l0b (); // default
endinterface
interface l2_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l2_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l1_if #(W*2, L0A_W) l1(); // derived
l1_if #(W * 2, L0A_W) l1 (); // derived
endinterface
interface l3_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l3_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l2_if #(W*2, L0A_W) l2a(); // derived
l2_if #(8, L0A_W) l2b(); // hard-coded
l2_if #(W * 2, L0A_W) l2a (); // derived
l2_if #(8, L0A_W) l2b (); // hard-coded
endinterface
interface l4_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l4_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l3_if #(W*2, L0A_W) l3(); // derived
l3_if #(W * 2, L0A_W) l3 (); // derived
endinterface
// Handlers use unparameterized interface ports with parameterized output widths
module l0_handler #(parameter int W = 8)(
input logic clk,
l0_if l0,
output logic [W-1:0] dout
module l0_handler #(
parameter int W = 8
) (
input logic clk,
l0_if l0,
output logic [W-1:0] dout
);
always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ W'('1);
assign dout = l0.dut_out;
endmodule
module l1_reader #(parameter int W = 8)(
l1_if l1,
output logic [W-1:0] dout
module l1_reader #(
parameter int W = 8
) (
l1_if l1,
output logic [W-1:0] dout
);
assign dout = l1.dut_out;
endmodule
module l1_driver #(parameter int W = 8)(
input logic clk,
l1_if l1
module l1_driver #(
parameter int W = 8
) (
input logic clk,
l1_if l1
);
always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ W'('1);
endmodule
module l1_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l1_if l1,
output logic [W-1:0] l1_dout,
output logic [L0A_W-1:0] l0a_dout,
output logic [7:0] l0b_dout
module l1_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l1_if l1,
output logic [W-1:0] l1_dout,
output logic [L0A_W-1:0] l0a_dout,
output logic [7:0] l0b_dout
);
// Use reader/driver submodules instead of direct access
l1_reader #(W) m_rdr (.l1(l1), .dout(l1_dout));
l1_driver #(W) m_drv (.clk(clk), .l1(l1));
l1_reader #(W) m_rdr (
.l1(l1),
.dout(l1_dout)
);
l1_driver #(W) m_drv (
.clk(clk),
.l1(l1)
);
// Still instantiate l0_handlers for nested ports
l0_handler #(L0A_W) m_l0a (.clk(clk), .l0(l1.l0a), .dout(l0a_dout));
l0_handler #(8) m_l0b (.clk(clk), .l0(l1.l0b), .dout(l0b_dout));
endmodule
module l2_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l2_if l2,
output logic [W-1:0] l2_dout,
output logic [W*2-1:0] l1_dout,
output logic [L0A_W-1:0] l0a_dout,
output logic [7:0] l0b_dout
);
always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ W'('1);
assign l2_dout = l2.dut_out;
l1_handler #(W*2, L0A_W) m_l1 (
.clk(clk), .l1(l2.l1),
.l1_dout(l1_dout), .l0a_dout(l0a_dout), .l0b_dout(l0b_dout)
l0_handler #(L0A_W) m_l0a (
.clk(clk),
.l0(l1.l0a),
.dout(l0a_dout)
);
l0_handler #(8) m_l0b (
.clk(clk),
.l0(l1.l0b),
.dout(l0b_dout)
);
endmodule
module l3_reader #(parameter int W = 8)(
l3_if l3,
output logic [W-1:0] dout
module l2_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l2_if l2,
output logic [W-1:0] l2_dout,
output logic [W*2-1:0] l1_dout,
output logic [L0A_W-1:0] l0a_dout,
output logic [7:0] l0b_dout
);
always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ W'('1);
assign l2_dout = l2.dut_out;
l1_handler #(W * 2, L0A_W) m_l1 (
.clk(clk),
.l1(l2.l1),
.l1_dout(l1_dout),
.l0a_dout(l0a_dout),
.l0b_dout(l0b_dout)
);
endmodule
module l3_reader #(
parameter int W = 8
) (
l3_if l3,
output logic [W-1:0] dout
);
assign dout = l3.dut_out;
endmodule
module l3_driver #(parameter int W = 8)(
input logic clk,
l3_if l3
module l3_driver #(
parameter int W = 8
) (
input logic clk,
l3_if l3
);
always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ W'('1);
endmodule
module l3_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l3_if l3,
output logic [W-1:0] l3_dout,
output logic [W*2-1:0] l2a_dout,
output logic [W*4-1:0] l1_2a_dout,
output logic [L0A_W-1:0] l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output logic [L0A_W-1:0] l0a_2b_dout,
output logic [7:0] l0b_2b_dout
module l3_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l3_if l3,
output logic [W-1:0] l3_dout,
output logic [W*2-1:0] l2a_dout,
output logic [W*4-1:0] l1_2a_dout,
output logic [L0A_W-1:0] l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output logic [L0A_W-1:0] l0a_2b_dout,
output logic [7:0] l0b_2b_dout
);
// Use reader/driver submodules instead of direct access
l3_reader #(W) m_rdr (.l3(l3), .dout(l3_dout));
l3_driver #(W) m_drv (.clk(clk), .l3(l3));
l3_reader #(W) m_rdr (
.l3(l3),
.dout(l3_dout)
);
l3_driver #(W) m_drv (
.clk(clk),
.l3(l3)
);
// Still instantiate l2_handlers for nested ports
l2_handler #(W*2, L0A_W) m_l2a (
.clk(clk), .l2(l3.l2a),
.l2_dout(l2a_dout), .l1_dout(l1_2a_dout),
.l0a_dout(l0a_2a_dout), .l0b_dout(l0b_2a_dout)
l2_handler #(W * 2, L0A_W) m_l2a (
.clk(clk),
.l2(l3.l2a),
.l2_dout(l2a_dout),
.l1_dout(l1_2a_dout),
.l0a_dout(l0a_2a_dout),
.l0b_dout(l0b_2a_dout)
);
l2_handler #(8, L0A_W) m_l2b (
.clk(clk), .l2(l3.l2b),
.l2_dout(l2b_dout), .l1_dout(l1_2b_dout),
.l0a_dout(l0a_2b_dout), .l0b_dout(l0b_2b_dout)
.clk(clk),
.l2(l3.l2b),
.l2_dout(l2b_dout),
.l1_dout(l1_2b_dout),
.l0a_dout(l0a_2b_dout),
.l0b_dout(l0b_2b_dout)
);
endmodule
module l4_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l4_if l4,
output logic [W-1:0] l4_dout,
output logic [W*2-1:0] l3_dout,
output logic [W*4-1:0] l2a_dout,
output logic [W*8-1:0] l1_2a_dout,
output logic [L0A_W-1:0] l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output logic [L0A_W-1:0] l0a_2b_dout,
output logic [7:0] l0b_2b_dout
module l4_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l4_if l4,
output logic [W-1:0] l4_dout,
output logic [W*2-1:0] l3_dout,
output logic [W*4-1:0] l2a_dout,
output logic [W*8-1:0] l1_2a_dout,
output logic [L0A_W-1:0] l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output logic [L0A_W-1:0] l0a_2b_dout,
output logic [7:0] l0b_2b_dout
);
always_ff @(posedge clk) l4.dut_out <= l4.tb_in ^ W'('1);
assign l4_dout = l4.dut_out;
l3_handler #(W*2, L0A_W) m_l3 (
.clk(clk), .l3(l4.l3),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout), .l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout), .l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout), .l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout), .l0b_2b_dout(l0b_2b_dout)
l3_handler #(W * 2, L0A_W) m_l3 (
.clk(clk),
.l3(l4.l3),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout),
.l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout),
.l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout),
.l0b_2b_dout(l0b_2b_dout)
);
endmodule
module t;
logic clk = 0;
int cyc = 0;
int cyc = 0;
localparam int TOP_W = 4;
localparam int L0A_W = 16;
l4_if #(TOP_W, L0A_W) inst();
l4_if #(TOP_W, L0A_W) inst ();
logic [TOP_W-1:0] l4_dout;
logic [TOP_W-1:0] l4_dout;
logic [TOP_W*2-1:0] l3_dout;
logic [TOP_W*4-1:0] l2a_dout;
logic [TOP_W*8-1:0] l1_2a_dout;
logic [L0A_W-1:0] l0a_2a_dout;
logic [7:0] l0b_2a_dout;
logic [7:0] l2b_dout;
logic [15:0] l1_2b_dout;
logic [L0A_W-1:0] l0a_2b_dout;
logic [7:0] l0b_2b_dout;
logic [L0A_W-1:0] l0a_2a_dout;
logic [7:0] l0b_2a_dout;
logic [7:0] l2b_dout;
logic [15:0] l1_2b_dout;
logic [L0A_W-1:0] l0a_2b_dout;
logic [7:0] l0b_2b_dout;
l4_handler #(TOP_W, L0A_W) m_l4 (
.clk(clk), .l4(inst),
.l4_dout(l4_dout),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout), .l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout), .l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout), .l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout), .l0b_2b_dout(l0b_2b_dout)
.clk(clk),
.l4(inst),
.l4_dout(l4_dout),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout),
.l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout),
.l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout),
.l0b_2b_dout(l0b_2b_dout)
);
always #5 clk = ~clk;
always_ff @(posedge clk) begin
inst.tb_in <= cyc[TOP_W-1:0];
inst.l3.tb_in <= cyc[TOP_W*2-1:0] + (TOP_W*2)'(1);
inst.l3.l2a.tb_in <= cyc[TOP_W*4-1:0] + (TOP_W*4)'(2);
inst.l3.l2a.l1.tb_in <= cyc[TOP_W*8-1:0] + (TOP_W*8)'(3);
inst.tb_in <= cyc[TOP_W-1:0];
inst.l3.tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(1);
inst.l3.l2a.tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(2);
inst.l3.l2a.l1.tb_in <= cyc[TOP_W*8-1:0] + (TOP_W * 8)'(3);
inst.l3.l2a.l1.l0a.tb_in <= cyc[L0A_W-1:0] + L0A_W'(4);
inst.l3.l2a.l1.l0b.tb_in <= cyc[7:0] + 8'd5;
inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6;
inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7;
inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6;
inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7;
inst.l3.l2b.l1.l0a.tb_in <= cyc[L0A_W-1:0] + L0A_W'(8);
inst.l3.l2b.l1.l0b.tb_in <= cyc[7:0] + 8'd9;
end
logic [TOP_W-1:0] exp_l4;
logic [TOP_W-1:0] exp_l4;
logic [TOP_W*2-1:0] exp_l3;
logic [TOP_W*4-1:0] exp_l2a;
logic [TOP_W*8-1:0] exp_l1_2a;
logic [L0A_W-1:0] exp_l0a_2a;
logic [7:0] exp_l0b_2a;
logic [7:0] exp_l2b;
logic [15:0] exp_l1_2b;
logic [L0A_W-1:0] exp_l0a_2b;
logic [7:0] exp_l0b_2b;
logic [L0A_W-1:0] exp_l0a_2a;
logic [7:0] exp_l0b_2a;
logic [7:0] exp_l2b;
logic [15:0] exp_l1_2b;
logic [L0A_W-1:0] exp_l0a_2b;
logic [7:0] exp_l0b_2b;
always_ff @(posedge clk) begin
exp_l4 <= inst.tb_in ^ TOP_W'('1);
exp_l3 <= inst.l3.tb_in ^ (TOP_W*2)'('1);
exp_l2a <= inst.l3.l2a.tb_in ^ (TOP_W*4)'('1);
exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ (TOP_W*8)'('1);
exp_l4 <= inst.tb_in ^ TOP_W'('1);
exp_l3 <= inst.l3.tb_in ^ (TOP_W * 2)'('1);
exp_l2a <= inst.l3.l2a.tb_in ^ (TOP_W * 4)'('1);
exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ (TOP_W * 8)'('1);
exp_l0a_2a <= inst.l3.l2a.l1.l0a.tb_in ^ L0A_W'('1);
exp_l0b_2a <= inst.l3.l2a.l1.l0b.tb_in ^ 8'hFF;
exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF;
exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF;
exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF;
exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF;
exp_l0a_2b <= inst.l3.l2b.l1.l0a.tb_in ^ L0A_W'('1);
exp_l0b_2b <= inst.l3.l2b.l1.l0b.tb_in ^ 8'hFF;
end

28
test_regress/t/t_interface_nested_port_array.out
View File

@ -1,24 +1,24 @@
%Error: t/t_interface_nested_port_array.v:111:3: Interface 'l3_if' not connected as parent's interface not connected
%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
111 | l3_if #(W, L0A_W) l3,
| ^~~~~
160 | l3_if#(W, L0A_W) l3,
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_nested_port_array.v:83:3: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
83 | l2_if #(W, L0A_W) l2s[1:0],
| ^~~~~
%Error: t/t_interface_nested_port_array.v:60:3: Interface 'l2_if' not connected as parent's interface not connected
%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
123 | l2_if#(W, L0A_W) l2s[1:0],
| ^~~~~
%Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2.m_l2b'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
60 | l2_if #(W, L0A_W) l2,
| ^~~~~
%Error: Internal Error: t/t_interface_nested_port_array.v:22:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry?
91 | l2_if#(W, L0A_W) l2,
| ^~~~~
%Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry?
: ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1'
22 | interface l2_if #(parameter int W = 8, parameter int L0A_W = 8);
27 | interface l2_if #(
| ^~~~~
... This fatal error may be caused by the earlier error(s); resolve those first.

333
test_regress/t/t_interface_nested_port_array.v
View File

@ -7,163 +7,222 @@
// Issue #5066 - Nested interface ports through interface arrays
// Similar structure to t_interface_nested_port.v, but with interface arrays.
interface l0_if #(parameter int W = 8);
interface l0_if #(
parameter int W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
endinterface
interface l1_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l1_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l0_if #(L0A_W) l0a[1:0](); // arrayed passthrough
l0_if l0b(); // default
l0_if #(L0A_W) l0a[1:0] (); // arrayed passthrough
l0_if l0b (); // default
endinterface
interface l2_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l2_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l1_if #(W*2, L0A_W) l1[1:0](); // derived
l1_if #(W * 2, L0A_W) l1[1:0] (); // derived
endinterface
interface l3_if #(parameter int W = 8, parameter int L0A_W = 8);
interface l3_if #(
parameter int W = 8,
parameter int L0A_W = 8
);
logic [W-1:0] tb_in;
logic [W-1:0] dut_out;
l2_if #(W*2, L0A_W) l2[1:0](); // arrayed
l2_if #(W * 2, L0A_W) l2[1:0] (); // arrayed
endinterface
module l0_handler #(parameter int W = 8)(
input logic clk,
l0_if #(W) l0,
output logic [W-1:0] dout
module l0_handler #(
parameter int W = 8
) (
input logic clk,
l0_if#(W) l0,
output logic [W-1:0] dout
);
always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ W'('1);
assign dout = l0.dut_out;
endmodule
module l1_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l1_if #(W, L0A_W) l1,
output logic [W-1:0] l1_dout,
output logic [L0A_W-1:0] l0a0_dout,
output logic [L0A_W-1:0] l0a1_dout,
output logic [7:0] l0b_dout
module l1_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l1_if#(W, L0A_W) l1,
output logic [W-1:0] l1_dout,
output logic [L0A_W-1:0] l0a0_dout,
output logic [L0A_W-1:0] l0a1_dout,
output logic [7:0] l0b_dout
);
always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ W'('1);
assign l1_dout = l1.dut_out;
l0_handler #(L0A_W) m_l0a0 (.clk(clk), .l0(l1.l0a[0]), .dout(l0a0_dout));
l0_handler #(L0A_W) m_l0a1 (.clk(clk), .l0(l1.l0a[1]), .dout(l0a1_dout));
l0_handler #(8) m_l0b (.clk(clk), .l0(l1.l0b), .dout(l0b_dout));
l0_handler #(L0A_W) m_l0a0 (
.clk(clk),
.l0(l1.l0a[0]),
.dout(l0a0_dout)
);
l0_handler #(L0A_W) m_l0a1 (
.clk(clk),
.l0(l1.l0a[1]),
.dout(l0a1_dout)
);
l0_handler #(8) m_l0b (
.clk(clk),
.l0(l1.l0b),
.dout(l0b_dout)
);
endmodule
module l2_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l2_if #(W, L0A_W) l2,
output logic [W-1:0] l2_dout,
output logic [W*2-1:0] l1_0_dout,
output logic [L0A_W-1:0] l0a0_0_dout,
output logic [L0A_W-1:0] l0a1_1_dout,
output logic [7:0] l0b_1_dout
module l2_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l2_if#(W, L0A_W) l2,
output logic [W-1:0] l2_dout,
output logic [W*2-1:0] l1_0_dout,
output logic [L0A_W-1:0] l0a0_0_dout,
output logic [L0A_W-1:0] l0a1_1_dout,
output logic [7:0] l0b_1_dout
);
always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ W'('1);
assign l2_dout = l2.dut_out;
l1_handler #(W*2, L0A_W) m_l1_0 (
.clk(clk), .l1(l2.l1[0]),
.l1_dout(l1_0_dout), .l0a0_dout(l0a0_0_dout),
.l0a1_dout(), .l0b_dout()
l1_handler #(W * 2, L0A_W) m_l1_0 (
.clk(clk),
.l1(l2.l1[0]),
.l1_dout(l1_0_dout),
.l0a0_dout(l0a0_0_dout),
.l0a1_dout(),
.l0b_dout()
);
l1_handler #(W*2, L0A_W) m_l1_1 (
.clk(clk), .l1(l2.l1[1]),
.l1_dout(), .l0a0_dout(),
.l0a1_dout(l0a1_1_dout), .l0b_dout(l0b_1_dout)
l1_handler #(W * 2, L0A_W) m_l1_1 (
.clk(clk),
.l1(l2.l1[1]),
.l1_dout(),
.l0a0_dout(),
.l0a1_dout(l0a1_1_dout),
.l0b_dout(l0b_1_dout)
);
endmodule
module l2_array_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l2_if #(W, L0A_W) l2s[1:0],
output logic [W-1:0] l2a_dout,
output logic [W*2-1:0] l2a_l1_0_dout,
output logic [L0A_W-1:0] l2a_l0a0_0_dout,
output logic [L0A_W-1:0] l2a_l0a1_1_dout,
output logic [7:0] l2a_l0b_1_dout,
output logic [W-1:0] l2b_dout,
output logic [W*2-1:0] l2b_l1_0_dout,
output logic [L0A_W-1:0] l2b_l0a0_0_dout,
output logic [L0A_W-1:0] l2b_l0a1_1_dout,
output logic [7:0] l2b_l0b_1_dout
module l2_array_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l2_if#(W, L0A_W) l2s[1:0],
output logic [W-1:0] l2a_dout,
output logic [W*2-1:0] l2a_l1_0_dout,
output logic [L0A_W-1:0] l2a_l0a0_0_dout,
output logic [L0A_W-1:0] l2a_l0a1_1_dout,
output logic [7:0] l2a_l0b_1_dout,
output logic [W-1:0] l2b_dout,
output logic [W*2-1:0] l2b_l1_0_dout,
output logic [L0A_W-1:0] l2b_l0a0_0_dout,
output logic [L0A_W-1:0] l2b_l0a1_1_dout,
output logic [7:0] l2b_l0b_1_dout
);
l2_handler #(W, L0A_W) m_l2a (
.clk(clk), .l2(l2s[0]),
.l2_dout(l2a_dout),
.l1_0_dout(l2a_l1_0_dout), .l0a0_0_dout(l2a_l0a0_0_dout),
.l0a1_1_dout(l2a_l0a1_1_dout), .l0b_1_dout(l2a_l0b_1_dout)
.clk(clk),
.l2(l2s[0]),
.l2_dout(l2a_dout),
.l1_0_dout(l2a_l1_0_dout),
.l0a0_0_dout(l2a_l0a0_0_dout),
.l0a1_1_dout(l2a_l0a1_1_dout),
.l0b_1_dout(l2a_l0b_1_dout)
);
l2_handler #(W, L0A_W) m_l2b (
.clk(clk), .l2(l2s[1]),
.l2_dout(l2b_dout),
.l1_0_dout(l2b_l1_0_dout), .l0a0_0_dout(l2b_l0a0_0_dout),
.l0a1_1_dout(l2b_l0a1_1_dout), .l0b_1_dout(l2b_l0b_1_dout)
.clk(clk),
.l2(l2s[1]),
.l2_dout(l2b_dout),
.l1_0_dout(l2b_l1_0_dout),
.l0a0_0_dout(l2b_l0a0_0_dout),
.l0a1_1_dout(l2b_l0a1_1_dout),
.l0b_1_dout(l2b_l0b_1_dout)
);
endmodule
module l3_handler #(parameter int W = 8, parameter int L0A_W = 8)(
input logic clk,
l3_if #(W, L0A_W) l3,
output logic [W-1:0] l3_dout,
output logic [W*2-1:0] l2a_dout,
output logic [W*4-1:0] l2a_l1_0_dout,
output logic [L0A_W-1:0] l2a_l0a0_0_dout,
output logic [L0A_W-1:0] l2a_l0a1_1_dout,
output logic [7:0] l2a_l0b_1_dout,
output logic [W*2-1:0] l2b_dout,
output logic [W*4-1:0] l2b_l1_0_dout,
output logic [L0A_W-1:0] l2b_l0a0_0_dout,
output logic [L0A_W-1:0] l2b_l0a1_1_dout,
output logic [7:0] l2b_l0b_1_dout
module l3_handler #(
parameter int W = 8,
parameter int L0A_W = 8
) (
input logic clk,
l3_if#(W, L0A_W) l3,
output logic [W-1:0] l3_dout,
output logic [W*2-1:0] l2a_dout,
output logic [W*4-1:0] l2a_l1_0_dout,
output logic [L0A_W-1:0] l2a_l0a0_0_dout,
output logic [L0A_W-1:0] l2a_l0a1_1_dout,
output logic [7:0] l2a_l0b_1_dout,
output logic [W*2-1:0] l2b_dout,
output logic [W*4-1:0] l2b_l1_0_dout,
output logic [L0A_W-1:0] l2b_l0a0_0_dout,
output logic [L0A_W-1:0] l2b_l0a1_1_dout,
output logic [7:0] l2b_l0b_1_dout
);
always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ W'('1);
assign l3_dout = l3.dut_out;
l2_array_handler #(W*2, L0A_W) m_l2 (
.clk(clk), .l2s(l3.l2),
.l2a_dout(l2a_dout),
.l2a_l1_0_dout(l2a_l1_0_dout), .l2a_l0a0_0_dout(l2a_l0a0_0_dout),
.l2a_l0a1_1_dout(l2a_l0a1_1_dout), .l2a_l0b_1_dout(l2a_l0b_1_dout),
.l2b_dout(l2b_dout),
.l2b_l1_0_dout(l2b_l1_0_dout), .l2b_l0a0_0_dout(l2b_l0a0_0_dout),
.l2b_l0a1_1_dout(l2b_l0a1_1_dout), .l2b_l0b_1_dout(l2b_l0b_1_dout)
l2_array_handler #(W * 2, L0A_W) m_l2 (
.clk(clk),
.l2s(l3.l2),
.l2a_dout(l2a_dout),
.l2a_l1_0_dout(l2a_l1_0_dout),
.l2a_l0a0_0_dout(l2a_l0a0_0_dout),
.l2a_l0a1_1_dout(l2a_l0a1_1_dout),
.l2a_l0b_1_dout(l2a_l0b_1_dout),
.l2b_dout(l2b_dout),
.l2b_l1_0_dout(l2b_l1_0_dout),
.l2b_l0a0_0_dout(l2b_l0a0_0_dout),
.l2b_l0a1_1_dout(l2b_l0a1_1_dout),
.l2b_l0b_1_dout(l2b_l0b_1_dout)
);
endmodule
module t;
logic clk = 0;
int cyc = 0;
int cyc = 0;
localparam int TOP_W = 4;
localparam int L0A_W = 12;
l3_if #(TOP_W, L0A_W) inst();
l3_if #(TOP_W, L0A_W) inst ();
logic [TOP_W-1:0] l3_dout;
logic [TOP_W*2-1:0] l2a_dout;
logic [TOP_W*4-1:0] l2a_l1_0_dout;
logic [L0A_W-1:0] l2a_l0a0_0_dout;
logic [L0A_W-1:0] l2a_l0a1_1_dout;
logic [7:0] l2a_l0b_1_dout;
logic [TOP_W*2-1:0] l2b_dout;
logic [TOP_W*4-1:0] l2b_l1_0_dout;
logic [L0A_W-1:0] l2b_l0a0_0_dout;
logic [L0A_W-1:0] l2b_l0a1_1_dout;
logic [7:0] l2b_l0b_1_dout;
logic [TOP_W-1:0] l3_dout;
logic [TOP_W*2-1:0] l2a_dout;
logic [TOP_W*4-1:0] l2a_l1_0_dout;
logic [L0A_W-1:0] l2a_l0a0_0_dout;
logic [L0A_W-1:0] l2a_l0a1_1_dout;
logic [7:0] l2a_l0b_1_dout;
logic [TOP_W*2-1:0] l2b_dout;
logic [TOP_W*4-1:0] l2b_l1_0_dout;
logic [L0A_W-1:0] l2b_l0a0_0_dout;
logic [L0A_W-1:0] l2b_l0a1_1_dout;
logic [7:0] l2b_l0b_1_dout;
l3_handler #(TOP_W, L0A_W) m_l3 (
.clk(clk), .l3(inst),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l2a_l1_0_dout(l2a_l1_0_dout), .l2a_l0a0_0_dout(l2a_l0a0_0_dout),
.l2a_l0a1_1_dout(l2a_l0a1_1_dout), .l2a_l0b_1_dout(l2a_l0b_1_dout),
.l2b_dout(l2b_dout),
.l2b_l1_0_dout(l2b_l1_0_dout), .l2b_l0a0_0_dout(l2b_l0a0_0_dout),
.l2b_l0a1_1_dout(l2b_l0a1_1_dout), .l2b_l0b_1_dout(l2b_l0b_1_dout)
.clk(clk),
.l3(inst),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l2a_l1_0_dout(l2a_l1_0_dout),
.l2a_l0a0_0_dout(l2a_l0a0_0_dout),
.l2a_l0a1_1_dout(l2a_l0a1_1_dout),
.l2a_l0b_1_dout(l2a_l0b_1_dout),
.l2b_dout(l2b_dout),
.l2b_l1_0_dout(l2b_l1_0_dout),
.l2b_l0a0_0_dout(l2b_l0a0_0_dout),
.l2b_l0a1_1_dout(l2b_l0a1_1_dout),
.l2b_l0b_1_dout(l2b_l0b_1_dout)
);
always #5 clk = ~clk;
@ -171,42 +230,42 @@ module t;
always_ff @(posedge clk) begin
inst.tb_in <= cyc[TOP_W-1:0];
inst.l2[0].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W*2)'(1);
inst.l2[0].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W*4)'(2);
inst.l2[0].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(1);
inst.l2[0].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(2);
inst.l2[0].l1[0].l0a[0].tb_in <= cyc[L0A_W-1:0] + L0A_W'(3);
inst.l2[0].l1[1].l0a[1].tb_in <= cyc[L0A_W-1:0] + L0A_W'(4);
inst.l2[0].l1[1].l0b.tb_in <= cyc[7:0] + 8'd5;
inst.l2[1].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W*2)'(6);
inst.l2[1].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W*4)'(7);
inst.l2[1].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(6);
inst.l2[1].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(7);
inst.l2[1].l1[0].l0a[0].tb_in <= cyc[L0A_W-1:0] + L0A_W'(8);
inst.l2[1].l1[1].l0a[1].tb_in <= cyc[L0A_W-1:0] + L0A_W'(9);
inst.l2[1].l1[1].l0b.tb_in <= cyc[7:0] + 8'd10;
end
logic [TOP_W-1:0] exp_l3_dout;
logic [TOP_W*2-1:0] exp_l2a_dout;
logic [TOP_W*4-1:0] exp_l2a_l1_0_dout;
logic [L0A_W-1:0] exp_l2a_l0a0_0_dout;
logic [L0A_W-1:0] exp_l2a_l0a1_1_dout;
logic [7:0] exp_l2a_l0b_1_dout;
logic [TOP_W*2-1:0] exp_l2b_dout;
logic [TOP_W*4-1:0] exp_l2b_l1_0_dout;
logic [L0A_W-1:0] exp_l2b_l0a0_0_dout;
logic [L0A_W-1:0] exp_l2b_l0a1_1_dout;
logic [7:0] exp_l2b_l0b_1_dout;
logic [TOP_W-1:0] exp_l3_dout;
logic [TOP_W*2-1:0] exp_l2a_dout;
logic [TOP_W*4-1:0] exp_l2a_l1_0_dout;
logic [L0A_W-1:0] exp_l2a_l0a0_0_dout;
logic [L0A_W-1:0] exp_l2a_l0a1_1_dout;
logic [7:0] exp_l2a_l0b_1_dout;
logic [TOP_W*2-1:0] exp_l2b_dout;
logic [TOP_W*4-1:0] exp_l2b_l1_0_dout;
logic [L0A_W-1:0] exp_l2b_l0a0_0_dout;
logic [L0A_W-1:0] exp_l2b_l0a1_1_dout;
logic [7:0] exp_l2b_l0b_1_dout;
always_ff @(posedge clk) begin
exp_l3_dout <= inst.tb_in ^ TOP_W'('1);
exp_l2a_dout <= inst.l2[0].tb_in ^ (TOP_W*2)'('1);
exp_l2a_l1_0_dout <= inst.l2[0].l1[0].tb_in ^ (TOP_W*4)'('1);
exp_l2a_dout <= inst.l2[0].tb_in ^ (TOP_W * 2)'('1);
exp_l2a_l1_0_dout <= inst.l2[0].l1[0].tb_in ^ (TOP_W * 4)'('1);
exp_l2a_l0a0_0_dout <= inst.l2[0].l1[0].l0a[0].tb_in ^ L0A_W'('1);
exp_l2a_l0a1_1_dout <= inst.l2[0].l1[1].l0a[1].tb_in ^ L0A_W'('1);
exp_l2a_l0b_1_dout <= inst.l2[0].l1[1].l0b.tb_in ^ 8'hFF;
exp_l2b_dout <= inst.l2[1].tb_in ^ (TOP_W*2)'('1);
exp_l2b_l1_0_dout <= inst.l2[1].l1[0].tb_in ^ (TOP_W*4)'('1);
exp_l2b_dout <= inst.l2[1].tb_in ^ (TOP_W * 2)'('1);
exp_l2b_l1_0_dout <= inst.l2[1].l1[0].tb_in ^ (TOP_W * 4)'('1);
exp_l2b_l0a0_0_dout <= inst.l2[1].l1[0].l0a[0].tb_in ^ L0A_W'('1);
exp_l2b_l0a1_1_dout <= inst.l2[1].l1[1].l0a[1].tb_in ^ L0A_W'('1);
exp_l2b_l0b_1_dout <= inst.l2[1].l1[1].l0b.tb_in ^ 8'hFF;
@ -225,23 +284,23 @@ module t;
$stop;
end
if (l2a_l1_0_dout !== exp_l2a_l1_0_dout) begin
$display("FAIL cyc=%0d: l2a_l1_0_dout=%h expected %h",
cyc, l2a_l1_0_dout, exp_l2a_l1_0_dout);
$display("FAIL cyc=%0d: l2a_l1_0_dout=%h expected %h", cyc, l2a_l1_0_dout,
exp_l2a_l1_0_dout);
$stop;
end
if (l2a_l0a0_0_dout !== exp_l2a_l0a0_0_dout) begin
$display("FAIL cyc=%0d: l2a_l0a0_0_dout=%h expected %h",
cyc, l2a_l0a0_0_dout, exp_l2a_l0a0_0_dout);
$display("FAIL cyc=%0d: l2a_l0a0_0_dout=%h expected %h", cyc, l2a_l0a0_0_dout,
exp_l2a_l0a0_0_dout);
$stop;
end
if (l2a_l0a1_1_dout !== exp_l2a_l0a1_1_dout) begin
$display("FAIL cyc=%0d: l2a_l0a1_1_dout=%h expected %h",
cyc, l2a_l0a1_1_dout, exp_l2a_l0a1_1_dout);
$display("FAIL cyc=%0d: l2a_l0a1_1_dout=%h expected %h", cyc, l2a_l0a1_1_dout,
exp_l2a_l0a1_1_dout);
$stop;
end
if (l2a_l0b_1_dout !== exp_l2a_l0b_1_dout) begin
$display("FAIL cyc=%0d: l2a_l0b_1_dout=%h expected %h",
cyc, l2a_l0b_1_dout, exp_l2a_l0b_1_dout);
$display("FAIL cyc=%0d: l2a_l0b_1_dout=%h expected %h", cyc, l2a_l0b_1_dout,
exp_l2a_l0b_1_dout);
$stop;
end
@ -250,23 +309,23 @@ module t;
$stop;
end
if (l2b_l1_0_dout !== exp_l2b_l1_0_dout) begin
$display("FAIL cyc=%0d: l2b_l1_0_dout=%h expected %h",
cyc, l2b_l1_0_dout, exp_l2b_l1_0_dout);
$display("FAIL cyc=%0d: l2b_l1_0_dout=%h expected %h", cyc, l2b_l1_0_dout,
exp_l2b_l1_0_dout);
$stop;
end
if (l2b_l0a0_0_dout !== exp_l2b_l0a0_0_dout) begin
$display("FAIL cyc=%0d: l2b_l0a0_0_dout=%h expected %h",
cyc, l2b_l0a0_0_dout, exp_l2b_l0a0_0_dout);
$display("FAIL cyc=%0d: l2b_l0a0_0_dout=%h expected %h", cyc, l2b_l0a0_0_dout,
exp_l2b_l0a0_0_dout);
$stop;
end
if (l2b_l0a1_1_dout !== exp_l2b_l0a1_1_dout) begin
$display("FAIL cyc=%0d: l2b_l0a1_1_dout=%h expected %h",
cyc, l2b_l0a1_1_dout, exp_l2b_l0a1_1_dout);
$display("FAIL cyc=%0d: l2b_l0a1_1_dout=%h expected %h", cyc, l2b_l0a1_1_dout,
exp_l2b_l0a1_1_dout);
$stop;
end
if (l2b_l0b_1_dout !== exp_l2b_l0b_1_dout) begin
$display("FAIL cyc=%0d: l2b_l0b_1_dout=%h expected %h",
cyc, l2b_l0b_1_dout, exp_l2b_l0b_1_dout);
$display("FAIL cyc=%0d: l2b_l0b_1_dout=%h expected %h", cyc, l2b_l0b_1_dout,
exp_l2b_l0b_1_dout);
$stop;
end
end

28
test_regress/t/t_interface_nested_port_array_noinl.out
View File

@ -1,24 +1,24 @@
%Error: t/t_interface_nested_port_array.v:111:3: Interface 'l3_if' not connected as parent's interface not connected
%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
111 | l3_if #(W, L0A_W) l3,
| ^~~~~
160 | l3_if#(W, L0A_W) l3,
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_nested_port_array.v:83:3: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
83 | l2_if #(W, L0A_W) l2s[1:0],
| ^~~~~
%Error: t/t_interface_nested_port_array.v:60:3: Interface 'l2_if' not connected as parent's interface not connected
%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
123 | l2_if#(W, L0A_W) l2s[1:0],
| ^~~~~
%Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected
: ... note: In instance 't.m_l3.m_l2.m_l2b'
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
60 | l2_if #(W, L0A_W) l2,
| ^~~~~
%Error: Internal Error: t/t_interface_nested_port_array.v:22:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry?
91 | l2_if#(W, L0A_W) l2,
| ^~~~~
%Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry?
: ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1'
22 | interface l2_if #(parameter int W = 8, parameter int L0A_W = 8);
27 | interface l2_if #(
| ^~~~~
... This fatal error may be caused by the earlier error(s); resolve those first.

369
test_regress/t/t_interface_nested_port_type.v
View File

@ -16,229 +16,346 @@
// L4(T=4b) -> L3(T=8b) -> L2A(T=16b) -> L1(T=32b) -> L0A(T=16b), L0B(T=8b)
// -> L2B(T=8b) -> L1(T=16b) -> L0A(T=16b), L0B(T=8b)
interface l0_if #(parameter type T = logic [7:0]);
interface l0_if #(
parameter type T = logic [7:0]
);
T tb_in;
T dut_out;
endinterface
interface l1_if #(parameter type T = logic, parameter type L0A_T = logic);
interface l1_if #(
parameter type T = logic,
parameter type L0A_T = logic
);
T tb_in;
T dut_out;
l0_if #(.T(L0A_T)) l0a(); // passthrough
l0_if l0b(); // default
l0_if #(.T(L0A_T)) l0a (); // passthrough
l0_if l0b (); // default
endinterface
interface l2_if #(parameter type T = logic, parameter type L0A_T = logic);
interface l2_if #(
parameter type T = logic,
parameter type L0A_T = logic
);
T tb_in;
T dut_out;
l1_if #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) l1(); // derived
l1_if #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) l1 (); // derived
endinterface
interface l3_if #(parameter type T = logic, parameter type L0A_T = logic);
interface l3_if #(
parameter type T = logic,
parameter type L0A_T = logic
);
T tb_in;
T dut_out;
l2_if #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) l2a(); // derived
l2_if #(.T(logic [7:0]), .L0A_T(L0A_T)) l2b(); // hard-coded
l2_if #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) l2a (); // derived
l2_if #(
.T(logic [7:0]),
.L0A_T(L0A_T)
) l2b (); // hard-coded
endinterface
interface l4_if #(parameter type T = logic, parameter type L0A_T = logic);
interface l4_if #(
parameter type T = logic,
parameter type L0A_T = logic
);
T tb_in;
T dut_out;
l3_if #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) l3(); // derived
l3_if #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) l3 (); // derived
endinterface
// Handlers use type parameters with derived output types
module l0_handler #(parameter type T = logic [7:0])(
input logic clk,
l0_if l0,
output T dout
module l0_handler #(
parameter type T = logic [7:0]
) (
input logic clk,
l0_if l0,
output T dout
);
always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ T'('1);
assign dout = l0.dut_out;
endmodule
module l1_reader #(parameter type T = logic)(
l1_if l1,
output T dout
module l1_reader #(
parameter type T = logic
) (
l1_if l1,
output T dout
);
assign dout = l1.dut_out;
endmodule
module l1_driver #(parameter type T = logic)(
input logic clk,
l1_if l1
module l1_driver #(
parameter type T = logic
) (
input logic clk,
l1_if l1
);
always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ T'('1);
endmodule
module l1_handler #(parameter type T = logic, parameter type L0A_T = logic)(
input logic clk,
l1_if l1,
output T l1_dout,
output L0A_T l0a_dout,
output logic [7:0] l0b_dout
module l1_handler #(
parameter type T = logic,
parameter type L0A_T = logic
) (
input logic clk,
l1_if l1,
output T l1_dout,
output L0A_T l0a_dout,
output logic [7:0] l0b_dout
);
// Use reader/driver submodules instead of direct access
l1_reader #(.T(T)) m_rdr (.l1(l1), .dout(l1_dout));
l1_driver #(.T(T)) m_drv (.clk(clk), .l1(l1));
l1_reader #(
.T(T)
) m_rdr (
.l1(l1),
.dout(l1_dout)
);
l1_driver #(
.T(T)
) m_drv (
.clk(clk),
.l1(l1)
);
// Still instantiate l0_handlers for nested ports
l0_handler #(.T(L0A_T)) m_l0a (.clk(clk), .l0(l1.l0a), .dout(l0a_dout));
l0_handler #(.T(logic [7:0])) m_l0b (.clk(clk), .l0(l1.l0b), .dout(l0b_dout));
endmodule
module l2_handler #(parameter type T = logic, parameter type L0A_T = logic)(
input logic clk,
l2_if l2,
output T l2_dout,
output logic [$bits(T)*2-1:0] l1_dout,
output L0A_T l0a_dout,
output logic [7:0] l0b_dout
);
always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ T'('1);
assign l2_dout = l2.dut_out;
l1_handler #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) m_l1 (
.clk(clk), .l1(l2.l1),
.l1_dout(l1_dout), .l0a_dout(l0a_dout), .l0b_dout(l0b_dout)
l0_handler #(
.T(L0A_T)
) m_l0a (
.clk(clk),
.l0(l1.l0a),
.dout(l0a_dout)
);
l0_handler #(
.T(logic [7:0])
) m_l0b (
.clk(clk),
.l0(l1.l0b),
.dout(l0b_dout)
);
endmodule
module l3_reader #(parameter type T = logic)(
l3_if l3,
output T dout
module l2_handler #(
parameter type T = logic,
parameter type L0A_T = logic
) (
input logic clk,
l2_if l2,
output T l2_dout,
output logic [$bits(T)*2-1:0] l1_dout,
output L0A_T l0a_dout,
output logic [7:0] l0b_dout
);
always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ T'('1);
assign l2_dout = l2.dut_out;
l1_handler #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) m_l1 (
.clk(clk),
.l1(l2.l1),
.l1_dout(l1_dout),
.l0a_dout(l0a_dout),
.l0b_dout(l0b_dout)
);
endmodule
module l3_reader #(
parameter type T = logic
) (
l3_if l3,
output T dout
);
assign dout = l3.dut_out;
endmodule
module l3_driver #(parameter type T = logic)(
input logic clk,
l3_if l3
module l3_driver #(
parameter type T = logic
) (
input logic clk,
l3_if l3
);
always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ T'('1);
endmodule
module l3_handler #(parameter type T = logic, parameter type L0A_T = logic)(
input logic clk,
l3_if l3,
output T l3_dout,
output logic [$bits(T)*2-1:0] l2a_dout,
output logic [$bits(T)*4-1:0] l1_2a_dout,
output L0A_T l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output L0A_T l0a_2b_dout,
output logic [7:0] l0b_2b_dout
module l3_handler #(
parameter type T = logic,
parameter type L0A_T = logic
) (
input logic clk,
l3_if l3,
output T l3_dout,
output logic [$bits(T)*2-1:0] l2a_dout,
output logic [$bits(T)*4-1:0] l1_2a_dout,
output L0A_T l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output L0A_T l0a_2b_dout,
output logic [7:0] l0b_2b_dout
);
// Use reader/driver submodules instead of direct access
l3_reader #(.T(T)) m_rdr (.l3(l3), .dout(l3_dout));
l3_driver #(.T(T)) m_drv (.clk(clk), .l3(l3));
l3_reader #(
.T(T)
) m_rdr (
.l3(l3),
.dout(l3_dout)
);
l3_driver #(
.T(T)
) m_drv (
.clk(clk),
.l3(l3)
);
// Still instantiate l2_handlers for nested ports
l2_handler #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) m_l2a (
.clk(clk), .l2(l3.l2a),
.l2_dout(l2a_dout), .l1_dout(l1_2a_dout),
.l0a_dout(l0a_2a_dout), .l0b_dout(l0b_2a_dout)
l2_handler #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) m_l2a (
.clk(clk),
.l2(l3.l2a),
.l2_dout(l2a_dout),
.l1_dout(l1_2a_dout),
.l0a_dout(l0a_2a_dout),
.l0b_dout(l0b_2a_dout)
);
l2_handler #(.T(logic [7:0]), .L0A_T(L0A_T)) m_l2b (
.clk(clk), .l2(l3.l2b),
.l2_dout(l2b_dout), .l1_dout(l1_2b_dout),
.l0a_dout(l0a_2b_dout), .l0b_dout(l0b_2b_dout)
l2_handler #(
.T(logic [7:0]),
.L0A_T(L0A_T)
) m_l2b (
.clk(clk),
.l2(l3.l2b),
.l2_dout(l2b_dout),
.l1_dout(l1_2b_dout),
.l0a_dout(l0a_2b_dout),
.l0b_dout(l0b_2b_dout)
);
endmodule
module l4_handler #(parameter type T = logic, parameter type L0A_T = logic)(
input logic clk,
l4_if l4,
output T l4_dout,
output logic [$bits(T)*2-1:0] l3_dout,
output logic [$bits(T)*4-1:0] l2a_dout,
output logic [$bits(T)*8-1:0] l1_2a_dout,
output L0A_T l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output L0A_T l0a_2b_dout,
output logic [7:0] l0b_2b_dout
module l4_handler #(
parameter type T = logic,
parameter type L0A_T = logic
) (
input logic clk,
l4_if l4,
output T l4_dout,
output logic [$bits(T)*2-1:0] l3_dout,
output logic [$bits(T)*4-1:0] l2a_dout,
output logic [$bits(T)*8-1:0] l1_2a_dout,
output L0A_T l0a_2a_dout,
output logic [7:0] l0b_2a_dout,
output logic [7:0] l2b_dout,
output logic [15:0] l1_2b_dout,
output L0A_T l0a_2b_dout,
output logic [7:0] l0b_2b_dout
);
always_ff @(posedge clk) l4.dut_out <= l4.tb_in ^ T'('1);
assign l4_dout = l4.dut_out;
l3_handler #(.T(logic [$bits(T)*2-1:0]), .L0A_T(L0A_T)) m_l3 (
.clk(clk), .l3(l4.l3),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout), .l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout), .l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout), .l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout), .l0b_2b_dout(l0b_2b_dout)
l3_handler #(
.T(logic [$bits(T)*2-1:0]),
.L0A_T(L0A_T)
) m_l3 (
.clk(clk),
.l3(l4.l3),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout),
.l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout),
.l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout),
.l0b_2b_dout(l0b_2b_dout)
);
endmodule
module t;
logic clk = 0;
int cyc = 0;
int cyc = 0;
localparam type TOP_T = logic [3:0];
localparam type L0A_T = logic [15:0];
l4_if #(.T(TOP_T), .L0A_T(L0A_T)) inst();
l4_if #(
.T(TOP_T),
.L0A_T(L0A_T)
) inst ();
logic [3:0] l4_dout;
logic [7:0] l3_dout;
logic [3:0] l4_dout;
logic [7:0] l3_dout;
logic [15:0] l2a_dout;
logic [31:0] l1_2a_dout;
logic [15:0] l0a_2a_dout;
logic [7:0] l0b_2a_dout;
logic [7:0] l2b_dout;
logic [7:0] l0b_2a_dout;
logic [7:0] l2b_dout;
logic [15:0] l1_2b_dout;
logic [15:0] l0a_2b_dout;
logic [7:0] l0b_2b_dout;
logic [7:0] l0b_2b_dout;
l4_handler #(.T(TOP_T), .L0A_T(L0A_T)) m_l4 (
.clk(clk), .l4(inst),
.l4_dout(l4_dout),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout), .l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout), .l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout), .l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout), .l0b_2b_dout(l0b_2b_dout)
l4_handler #(
.T(TOP_T),
.L0A_T(L0A_T)
) m_l4 (
.clk(clk),
.l4(inst),
.l4_dout(l4_dout),
.l3_dout(l3_dout),
.l2a_dout(l2a_dout),
.l1_2a_dout(l1_2a_dout),
.l0a_2a_dout(l0a_2a_dout),
.l0b_2a_dout(l0b_2a_dout),
.l2b_dout(l2b_dout),
.l1_2b_dout(l1_2b_dout),
.l0a_2b_dout(l0a_2b_dout),
.l0b_2b_dout(l0b_2b_dout)
);
always #5 clk = ~clk;
always_ff @(posedge clk) begin
inst.tb_in <= cyc[3:0];
inst.l3.tb_in <= cyc[7:0] + 8'd1;
inst.l3.l2a.tb_in <= cyc[15:0] + 16'd2;
inst.l3.l2a.l1.tb_in <= cyc[31:0] + 32'd3;
inst.tb_in <= cyc[3:0];
inst.l3.tb_in <= cyc[7:0] + 8'd1;
inst.l3.l2a.tb_in <= cyc[15:0] + 16'd2;
inst.l3.l2a.l1.tb_in <= cyc[31:0] + 32'd3;
inst.l3.l2a.l1.l0a.tb_in <= cyc[15:0] + 16'd4;
inst.l3.l2a.l1.l0b.tb_in <= cyc[7:0] + 8'd5;
inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6;
inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7;
inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6;
inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7;
inst.l3.l2b.l1.l0a.tb_in <= cyc[15:0] + 16'd8;
inst.l3.l2b.l1.l0b.tb_in <= cyc[7:0] + 8'd9;
end
logic [3:0] exp_l4;
logic [7:0] exp_l3;
logic [3:0] exp_l4;
logic [7:0] exp_l3;
logic [15:0] exp_l2a;
logic [31:0] exp_l1_2a;
logic [15:0] exp_l0a_2a;
logic [7:0] exp_l0b_2a;
logic [7:0] exp_l2b;
logic [7:0] exp_l0b_2a;
logic [7:0] exp_l2b;
logic [15:0] exp_l1_2b;
logic [15:0] exp_l0a_2b;
logic [7:0] exp_l0b_2b;
logic [7:0] exp_l0b_2b;
always_ff @(posedge clk) begin
exp_l4 <= inst.tb_in ^ 4'hF;
exp_l3 <= inst.l3.tb_in ^ 8'hFF;
exp_l2a <= inst.l3.l2a.tb_in ^ 16'hFFFF;
exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ 32'hFFFFFFFF;
exp_l4 <= inst.tb_in ^ 4'hF;
exp_l3 <= inst.l3.tb_in ^ 8'hFF;
exp_l2a <= inst.l3.l2a.tb_in ^ 16'hFFFF;
exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ 32'hFFFFFFFF;
exp_l0a_2a <= inst.l3.l2a.l1.l0a.tb_in ^ 16'hFFFF;
exp_l0b_2a <= inst.l3.l2a.l1.l0b.tb_in ^ 8'hFF;
exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF;
exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF;
exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF;
exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF;
exp_l0a_2b <= inst.l3.l2b.l1.l0a.tb_in ^ 16'hFFFF;
exp_l0b_2b <= inst.l3.l2b.l1.l0b.tb_in ^ 8'hFF;
end

2
test_regress/t/t_lparam_assign_iface_typedef4.v
View File

@ -15,7 +15,7 @@ endinterface
module top ();
x_if #(.a_width(8)) if0 ();
localparam type p0_t = if0.rq_t [1:0];
localparam type p0_t = if0.rq_t[1:0];
initial begin
if ($bits(p0_t) != 16) $stop;

18
test_regress/t/t_param_type_chain.v
View File

@ -4,16 +4,14 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
sub sub_default();
sub #(.foo_t (logic[7:0])) sub_8();
sub sub_default ();
sub #(.foo_t(logic [7:0])) sub_8 ();
always @ (posedge clk) begin
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
@ -21,8 +19,8 @@ module t (/*AUTOARG*/
endmodule
module sub #(
parameter type foo_t = logic,
parameter type bar_t = foo_t[1:0]
parameter type foo_t = logic,
parameter type bar_t = foo_t[1:0]
);
initial begin
$display("%m foo_t = %0d bar_t = %0d", $bits(foo_t), $bits(bar_t));

3
test_regress/t/t_randomize_struct_sel.v
View File

@ -20,7 +20,8 @@ module t;
if (o.randomize() == 0) begin
$display("Randomization failed");
$stop;
end else if (o.obj.x != o.rand_int) $stop;
end
else if (o.obj.x != o.rand_int) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

28
test_regress/t/t_scoped_rand_is_random.v
View File

@ -1,22 +1,22 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2026 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2016 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t ();
reg a0 = 'x;
reg a1 = 'x;
reg a2 = 'x;
reg a3 = 'x;
reg a4 = 'x;
reg a5 = 'x;
reg a6 = 'x;
reg a7 = 'x;
reg a8 = 'x;
reg a9 = 'x;
reg a0 = 'x;
reg a1 = 'x;
reg a2 = 'x;
reg a3 = 'x;
reg a4 = 'x;
reg a5 = 'x;
reg a6 = 'x;
reg a7 = 'x;
reg a8 = 'x;
reg a9 = 'x;
reg a10 = 'x;
reg a11 = 'x;
reg a12 = 'x;
@ -26,8 +26,8 @@ module t ();
integer fd;
initial begin
fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/bits.log"}, "a");
$fwrite(fd, "%b\n", {a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15});
fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/bits.log"}, "a");
$fwrite(fd, "%b\n", {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15});
$write("*-* All Finished *-*\n");
$finish;
end