Fix bounds checking in non-inlined function (#6677)

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Geza Lore 2025-11-11 11:47:49 +00:00 committed by GitHub
parent eb40c24b78
commit c5f8656aa0
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3 changed files with 25 additions and 10 deletions

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@ -65,6 +65,16 @@ class UnknownVisitor final : public VNVisitor {
// METHODS
void addVar(AstVar* varp) {
if (m_ftaskp) {
varp->funcLocal(true);
varp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
m_ftaskp->stmtsp()->addHereThisAsNext(varp);
} else {
m_modp->stmtsp()->addHereThisAsNext(varp);
}
}
void replaceBoundLvalue(AstNodeExpr* nodep, AstNodeExpr* condp) {
// Spec says a out-of-range LHS SEL results in a NOP.
// This is a PITA. We could:
@ -113,7 +123,7 @@ class UnknownVisitor final : public VNVisitor {
} else {
AstVar* const varp
= new AstVar{fl, VVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep()};
m_modp->addStmtsp(varp);
addVar(varp);
AstNode* stmtp = prep->backp(); // Grab above point before we replace 'prep'
while (!VN_IS(stmtp, NodeStmt)) stmtp = stmtp->backp();
@ -137,13 +147,7 @@ class UnknownVisitor final : public VNVisitor {
AstVar* createAddTemp(const AstNodeExpr* const nodep) {
AstVar* const varp = new AstVar{nodep->fileline(), VVarType::XTEMP,
m_xrandNames->get(nodep), nodep->dtypep()};
if (m_ftaskp) {
varp->funcLocal(true);
varp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
m_ftaskp->stmtsp()->addHereThisAsNext(varp);
} else {
m_modp->stmtsp()->addHereThisAsNext(varp);
}
addVar(varp);
return varp;
}

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@ -13,6 +13,6 @@ test.scenarios('vlt')
test.compile(verilator_flags2=['--stats'], verilator_make_gmake=False)
test.file_grep(test.stats, r'Optimizations, Functions inlined\s+(\d+)', 2)
test.file_grep(test.stats, r'Optimizations, Functions inlined\s+(\d+)', 3)
test.passes()

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@ -4,7 +4,11 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
module t(
input logic [16:0] clearBit_i,
input int clearBit_idx,
output logic [16:0] clearBit_o
);
function void allfin;
$write("*-* All Finished *-*\n");
@ -18,4 +22,11 @@ module t;
allfin();
done();
end
function automatic logic [16:0] clearBit(logic [16:0] i, int idx);
i[idx] = 1'b0;
return i;
endfunction
assign clearBit_o = clearBit(clearBit_i, clearBit_idx);
endmodule