Verilog format

test_regress/t/t_constraint_non_const_exp_pow_unsup.out

@@ -1,6 +1,6 @@
-%Warning-CONSTRAINTIGN: t/t_constraint_non_const_exp_pow_unsup.v:11:26: Unsupported: Power (**) expression with non-constant exponent in constraint
-   11 |   constraint c_power { x ** y < 10000; }
-      |                          ^~
+%Warning-CONSTRAINTIGN: t/t_constraint_non_const_exp_pow_unsup.v:11:25: Unsupported: Power (**) expression with non-constant exponent in constraint
+   11 |   constraint c_power {x ** y < 10000;}
+      |                         ^~
                         ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest
                         ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message.
 %Error: Exiting due to

test_regress/t/t_constraint_non_const_exp_pow_unsup.v

@@ -8,7 +8,7 @@ class Packet;
   rand int x;
   rand int y;
 
-  constraint c_power { x ** y < 10000; }
+  constraint c_power {x ** y < 10000;}
 endclass
 
 module t;

test_regress/t/t_flag_sched_zero_delay_none_bad.v

@@ -10,7 +10,7 @@ module top;
   int a = 1;
   initial begin
     #a;
-    a=2;
+    a = 2;
     #a;
   end
 endmodule

test_regress/t/t_flag_sched_zero_delay_off_run.out

@@ -1,6 +1,6 @@
 %Warning-ZERODLY: t/t_flag_sched_zero_delay_off_run.v:17:9: Static #0 delay exists, but '--no-sched-zero-delay' was given.
                                                           : ... Can proceed, but this will fail at runtime if executed.
-   17 |         #0;  
+   17 |         #0;   
       |         ^
                   ... For warning description see https://verilator.org/warn/ZERODLY?v=latest
                   ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message.

test_regress/t/t_flag_sched_zero_delay_off_run.v

@@ -14,7 +14,7 @@ module top;
       $display("%02t tick", $time);
       ++n;
       if (n > 5) begin
-        #0; // Will not execute
+        #0;  // Will not execute
         $stop;
       end
     end

test_regress/t/t_force_unpacked_struct.v

@@ -17,9 +17,9 @@ module t (
   integer cyc = 0;
 
   typedef struct {
-    int   x;
+    int x;
     logic y;
-    int  arr[5];
+    int arr[5];
   } struct_t;
 
   struct_t s_array[3];

test_regress/t/t_inside_impure_unsized.v

@@ -20,16 +20,16 @@ module t;
   initial begin
     str_arr["test"] = 25;
     str_key = "test";
-    if (!(str_arr[str_key] inside {[10:50]})) $stop;
-    if (str_arr[str_key] inside {[100:200]}) $stop;
+    if (!(str_arr[str_key] inside {[10 : 50]})) $stop;
+    if (str_arr[str_key] inside {[100 : 200]}) $stop;
 
     int_arr[0] = 25;
     int_key = 0;
-    if (!(int_arr[int_key] inside {[10:50]})) $stop;
-    if (int_arr[int_key] inside {[100:200]}) $stop;
+    if (!(int_arr[int_key] inside {[10 : 50]})) $stop;
+    if (int_arr[int_key] inside {[100 : 200]}) $stop;
 
-    if (!(get_val() inside {[10:50]})) $stop;
-    if (get_val() inside {[100:200]}) $stop;
+    if (!(get_val() inside {[10 : 50]})) $stop;
+    if (get_val() inside {[100 : 200]}) $stop;
 
     $write("*-* All Finished *-*\n");
     $finish;

test_regress/t/t_opt_life_dpi_written.v

@@ -4,8 +4,10 @@
 // SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (got), (exp)); `stop; end while(0)
+`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (got), (exp)); `stop; end while(0)
+// verilog_format: on
 
 module t;
 
@@ -14,7 +16,7 @@ module t;
     dpiSet = value;
   endfunction
   export "DPI-C" function setDpi;
-  import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value)
+  import "DPI-C" context function void setViaDpi(int value);  // calls setDpi(value)
 
   initial begin
     dpiSet = 13;

test_regress/t/t_randc_enum_constraint.v

@@ -15,22 +15,22 @@
 module t;
 
   typedef enum bit [2:0] {
-    RED   = 0,
+    RED = 0,
     GREEN = 1,
-    BLUE  = 2,
+    BLUE = 2,
     WHITE = 3,
     BLACK = 4
   } color_t;
 
   class ColorClass;
     randc color_t color;
-    constraint c_no_dark { color != BLACK; }
+    constraint c_no_dark {color != BLACK;}
   endclass
 
   // Test with all enum values allowed (no exclusion constraint)
   class AllColorsClass;
     randc color_t color;
-    constraint c_range { color <= WHITE; }
+    constraint c_range {color <= WHITE;}
   endclass
 
   initial begin

test_regress/t/t_randomize_null_object.v

@@ -12,7 +12,7 @@
 
 class SimpleRandClass;
   rand bit [7:0] value;
-  constraint value_con { value > 0 && value < 200; }
+  constraint value_con {value > 0 && value < 200;}
   function new();
   endfunction
 endclass

test_regress/t/t_randomize_unique_elem.v

@@ -16,17 +16,17 @@
 class UniqueElemSubset;
   rand bit [3:0] arr[10];
 
-  constraint unique_subset_con {
-    unique { arr[2], arr[3], arr[4], arr[5], arr[6] };
-  }
+  constraint unique_subset_con {unique {arr[2], arr[3], arr[4], arr[5], arr[6]};}
 
   function new();
   endfunction
 
   function bit check_unique();
-    for (int i = 2; i <= 6; i++)
-      for (int j = i + 1; j <= 6; j++)
+    for (int i = 2; i <= 6; i++) begin
+      for (int j = i + 1; j <= 6; j++) begin
         if (arr[i] == arr[j]) return 0;
+      end
+    end
     return 1;
   endfunction
 endclass
@@ -34,17 +34,17 @@ endclass
 class UniqueElemFour;
   rand bit [3:0] data[8];
 
-  constraint unique_data_con {
-    unique { data[1], data[2], data[3], data[4] };
-  }
+  constraint unique_data_con {unique {data[1], data[2], data[3], data[4]};}
 
   function new();
   endfunction
 
   function bit check_unique();
-    for (int i = 1; i <= 4; i++)
-      for (int j = i + 1; j <= 4; j++)
+    for (int i = 1; i <= 4; i++) begin
+      for (int j = i + 1; j <= 4; j++) begin
         if (data[i] == data[j]) return 0;
+      end
+    end
     return 1;
   endfunction
 endclass
@@ -52,9 +52,7 @@ endclass
 class UniqueElemSingle;
   rand bit [3:0] val[4];
 
-  constraint unique_single_con {
-    unique { val[0] };
-  }
+  constraint unique_single_con {unique {val[0]};}
 
   function new();
   endfunction

test_regress/t/t_scheduling_beforeTrig_life_opt.v

@@ -28,8 +28,8 @@ module t;
   reg clk, reset;
   wire done;
   s dut (
-      .clk  (clk),
-      .rdy  (done),
+      .clk(clk),
+      .rdy(done),
       .reset(reset)
   );
   always #5 clk = !clk;

test_regress/t/t_scheduling_zero_delay.v

@@ -6,8 +6,10 @@
 // SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: time=%t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: time=%t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+// verilog_format: on
 
 module top;
 

test_regress/t/t_wait.out

@@ -1,40 +1,40 @@
-%Error-NOTIMING: t/t_wait.v:12:7: Wait statements require --timing
+%Error-NOTIMING: t/t_wait.v:12:5: Wait statements require --timing
                                 : ... note: In instance 't'
-   12 |       wait (value == 1);
-      |       ^~~~
+   12 |     wait (value == 1);
+      |     ^~~~
                  ... For error description see https://verilator.org/warn/NOTIMING?v=latest
-%Error-NOTIMING: t/t_wait.v:14:7: Wait statements require --timing
+%Error-NOTIMING: t/t_wait.v:14:5: Wait statements require --timing
                                 : ... note: In instance 't'
-   14 |       wait (0);
-      |       ^~~~
-%Error-NOTIMING: t/t_wait.v:17:7: Wait statements require --timing
+   14 |     wait (0);
+      |     ^~~~
+%Error-NOTIMING: t/t_wait.v:17:5: Wait statements require --timing
                                 : ... note: In instance 't'
-   17 |       wait (value == 2);
-      |       ^~~~
-%Error-NOTIMING: t/t_wait.v:20:7: Wait statements require --timing
+   17 |     wait (value == 2);
+      |     ^~~~
+%Error-NOTIMING: t/t_wait.v:20:5: Wait statements require --timing
                                 : ... note: In instance 't'
-   20 |       wait (value == 3) if (value != 3) $stop;
-      |       ^~~~
-%Warning-STMTDLY: t/t_wait.v:25:7: Ignoring delay on this statement due to --no-timing
+   20 |     wait (value == 3) if (value != 3) $stop;
+      |     ^~~~
+%Warning-STMTDLY: t/t_wait.v:25:5: Ignoring delay on this statement due to --no-timing
                                  : ... note: In instance 't'
-   25 |       #10;
-      |       ^
+   25 |     #10;
+      |     ^
                   ... For warning description see https://verilator.org/warn/STMTDLY?v=latest
                   ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
-%Warning-STMTDLY: t/t_wait.v:27:7: Ignoring delay on this statement due to --no-timing
+%Warning-STMTDLY: t/t_wait.v:27:5: Ignoring delay on this statement due to --no-timing
                                  : ... note: In instance 't'
-   27 |       #10;
-      |       ^
-%Warning-STMTDLY: t/t_wait.v:29:7: Ignoring delay on this statement due to --no-timing
+   27 |     #10;
+      |     ^
+%Warning-STMTDLY: t/t_wait.v:29:5: Ignoring delay on this statement due to --no-timing
                                  : ... note: In instance 't'
-   29 |       #10;
-      |       ^
-%Warning-STMTDLY: t/t_wait.v:31:7: Ignoring delay on this statement due to --no-timing
+   29 |     #10;
+      |     ^
+%Warning-STMTDLY: t/t_wait.v:31:5: Ignoring delay on this statement due to --no-timing
                                  : ... note: In instance 't'
-   31 |       #10;
-      |       ^
-%Warning-STMTDLY: t/t_wait.v:33:7: Ignoring delay on this statement due to --no-timing
+   31 |     #10;
+      |     ^
+%Warning-STMTDLY: t/t_wait.v:33:5: Ignoring delay on this statement due to --no-timing
                                  : ... note: In instance 't'
-   33 |       #10;
-      |       ^
+   33 |     #10;
+      |     ^
 %Error: Exiting due to

test_regress/t/t_wait.v

@@ -6,33 +6,33 @@
 
 module t;
 
-   int value;
+  int value;
 
-   initial begin
-      wait (value == 1);
-      if (value != 1) $stop;
-      wait (0);
-      if (value != 1) $stop;
-      //
-      wait (value == 2);
-      if (value != 2) $stop;
-      //
-      wait (value == 3) if (value != 3) $stop;
-      if (value != 3) $stop;
-   end
+  initial begin
+    wait (value == 1);
+    if (value != 1) $stop;
+    wait (0);
+    if (value != 1) $stop;
+    //
+    wait (value == 2);
+    if (value != 2) $stop;
+    //
+    wait (value == 3) if (value != 3) $stop;
+    if (value != 3) $stop;
+  end
 
-   initial begin
-      #10;
-      value = 1;
-      #10;
-      value = 2;
-      #10;
-      value = 3;
-      #10;
-      value = 4;
-      #10;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    #10;
+    value = 1;
+    #10;
+    value = 2;
+    #10;
+    value = 3;
+    #10;
+    value = 4;
+    #10;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule

test_regress/t/t_wait_const.v

@@ -6,14 +6,14 @@
 
 module t;
 
-   initial begin
-      // This test is separate from t_wait.v because we needed a process with
-      // just one wait of a non-zero to see a bug where GCC gave "return value
-      // not used"
-      // verilator lint_off WAITCONST
-      wait (1);
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    // This test is separate from t_wait.v because we needed a process with
+    // just one wait of a non-zero to see a bug where GCC gave "return value
+    // not used"
+    // verilator lint_off WAITCONST
+    wait (1);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule

test_regress/t/t_wait_fork.v

@@ -6,20 +6,24 @@
 
 module t;
 
-   logic never;
+  logic never;
 
-   integer n = 0;
+  integer n = 0;
 
-   initial begin
-      disable fork;
-      fork
-         #10 if (n != 0) $stop; else n = 1;
-         #15 if (n != 1) $stop; else n = 2;
-      join_none
-      wait fork;
-      if (n != 2) $stop;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    disable fork;
+    fork
+      #10
+      if (n != 0) $stop;
+      else n = 1;
+      #15
+      if (n != 1) $stop;
+      else n = 2;
+    join_none
+    wait fork;
+    if (n != 2) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule

test_regress/t/t_wait_no_triggered_bad.out

@@ -1,7 +1,7 @@
-%Error: t/t_wait_no_triggered_bad.v:15:12: Wait statement conditions do not take raw events (IEEE 1800-2023 15.5.3)
+%Error: t/t_wait_no_triggered_bad.v:15:11: Wait statement conditions do not take raw events (IEEE 1800-2023 15.5.3)
                                          : ... note: In instance 't'
                                          : ... Suggest use 'e_my_event.triggered'
-   15 |       wait(e_my_event);   
-      |            ^~~~~~~~~~
+   15 |     wait (e_my_event);   
+      |           ^~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_wait_no_triggered_bad.v

@@ -6,16 +6,16 @@
 
 module t;
 
-   event e_my_event;
+  event e_my_event;
 
-   initial begin
-      #(1us);
-      wait(e_my_event.triggered);  // Ok
-      #(1us);
-      wait(e_my_event);  // Bad
+  initial begin
+    #(1us);
+    wait (e_my_event.triggered);  // Ok
+    #(1us);
+    wait (e_my_event);  // Bad
 
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule

test_regress/t/t_wait_order.out

@@ -1,17 +1,17 @@
-%Error-UNSUPPORTED: t/t_wait_order.v:17:23: Unsupported: wait_order
-   17 |       wait_order (a, b) wif[0] = '1;
-      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:19:21: Unsupported: wait_order
+   19 |     wait_order (a, b) wif[0] = '1;
+      |                     ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_wait_order.v:26:23: Unsupported: wait_order
-   26 |       wait_order (a, b) else welse[1] = '1;
-      |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:29:23: Unsupported: wait_order
-   29 |       wait_order (b, a) else nelse[1] = '1;
-      |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:33:23: Unsupported: wait_order
-   33 |       wait_order (a, b) wif[2] = '1; else welse[2] = '1;
-      |                       ^
-%Error-UNSUPPORTED: t/t_wait_order.v:36:23: Unsupported: wait_order
-   36 |       wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
-      |                       ^
+%Error-UNSUPPORTED: t/t_wait_order.v:28:21: Unsupported: wait_order
+   28 |     wait_order (a, b) else welse[1] = '1;
+      |                     ^
+%Error-UNSUPPORTED: t/t_wait_order.v:31:21: Unsupported: wait_order
+   31 |     wait_order (b, a) else nelse[1] = '1;
+      |                     ^
+%Error-UNSUPPORTED: t/t_wait_order.v:35:21: Unsupported: wait_order
+   35 |     wait_order (a, b) wif[2] = '1; else welse[2] = '1;
+      |                     ^
+%Error-UNSUPPORTED: t/t_wait_order.v:38:21: Unsupported: wait_order
+   38 |     wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
+      |                     ^
 %Error: Exiting due to

test_regress/t/t_wait_order.v

@@ -4,60 +4,62 @@
 // SPDX-FileCopyrightText: 2020 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 
-   event a, b, c;
-   bit   wif[10], welse[10];
-   bit   nif[10], nelse[10];
+  event a, b, c;
+  bit  wif[10], welse[10];
+  bit  nif[10], nelse[10];
 
-   initial begin
-      wait_order (a, b) wif[0] = '1;
-   end
+  initial begin
+    wait_order (a, b) wif[0] = '1;
+  end
 `ifdef FAIL_ASSERT_1
-   initial begin
-      wait_order (b, a) nif[0] = '1;
-   end
+  initial begin
+    wait_order (b, a) nif[0] = '1;
+  end
 `endif
 
-   initial begin
-      wait_order (a, b) else welse[1] = '1;
-   end
-   initial begin
-      wait_order (b, a) else nelse[1] = '1;
-   end
+  initial begin
+    wait_order (a, b) else welse[1] = '1;
+  end
+  initial begin
+    wait_order (b, a) else nelse[1] = '1;
+  end
 
-   initial begin
-      wait_order (a, b) wif[2] = '1; else welse[2] = '1;
-   end
-   initial begin
-      wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
-   end
+  initial begin
+    wait_order (a, b) wif[2] = '1; else welse[2] = '1;
+  end
+  initial begin
+    wait_order (b, a) nif[2] = '1; else nelse[2] = '1;
+  end
 
-   initial begin
-      #10;
-      -> a;
-      #10;
-      -> b;
-      #10;
-      -> c;
-      #10;
+  initial begin
+    #10;
+    -> a;
+    #10;
+    -> b;
+    #10;
+    -> c;
+    #10;
 
-      `checkd(wif[0], 1'b1);
-      `checkd(nif[0], 1'b0);
+    `checkd(wif[0], 1'b1);
+    `checkd(nif[0], 1'b0);
 
-      `checkd(welse[1], 1'b0);
-      `checkd(nelse[1], 1'b1);
+    `checkd(welse[1], 1'b0);
+    `checkd(nelse[1], 1'b1);
 
-      `checkd(wif[2], 1'b1);
-      `checkd(welse[2], 1'b0);
-      `checkd(nif[2], 1'b0);
-      `checkd(nelse[2], 1'b1);
+    `checkd(wif[2], 1'b1);
+    `checkd(welse[2], 1'b0);
+    `checkd(nif[2], 1'b0);
+    `checkd(nelse[2], 1'b1);
 
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 
 endmodule

test_regress/t/t_waiveroutput.v

@@ -5,11 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t_waiveroutput;
-   reg width_warn = 2'b11;  // Width warning - must be line 8
+  reg width_warn = 2'b11;  // Width warning - must be line 8
 
-   // verilator lint_off UNUSEDSIGNAL
-   // verilator lint_off WIDTHTRUNC
-   reg width_warn2 = 2'b11;
-   // verilator lint_on UNUSEDSIGNAL
-   // verilator lint_on WIDTHTRUNC
+  // verilator lint_off UNUSEDSIGNAL
+  // verilator lint_off WIDTHTRUNC
+  reg width_warn2 = 2'b11;
+  // verilator lint_on UNUSEDSIGNAL
+  // verilator lint_on WIDTHTRUNC
 endmodule

test_regress/t/t_waiveroutput_roundtrip.v

@@ -4,35 +4,39 @@
 // SPDX-FileCopyrightText: 2012 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
-   // Outputs
-   out, out2,
-   // Inputs
-   clk, a0, d0, d1
-   );
+module t (  /*AUTOARG*/
+    // Outputs
+    out,
+    out2,
+    // Inputs
+    clk,
+    a0,
+    d0,
+    d1
+);
 
-   input clk;
-   input [1:0] a0;
-   input [7:0] d0;
-   input [7:0] d1;
-   output reg [31:0] out;
-   output reg [15:0] out2;
+  input clk;
+  input [1:0] a0;
+  input [7:0] d0;
+  input [7:0] d1;
+  output reg [31:0] out;
+  output reg [15:0] out2;
 
-   reg [7:0]         mem [4];
+  reg [7:0] mem[4];
 
-   always @(posedge clk) begin
-      mem[a0] <= d0;  // <--- Warning
-   end
-   always @(negedge clk) begin
-      mem[a0] <= d1;  // <--- Warning
-   end
-   assign out = {mem[3],mem[2],mem[1],mem[0]};
+  always @(posedge clk) begin
+    mem[a0] <= d0;  // <--- Warning
+  end
+  always @(negedge clk) begin
+    mem[a0] <= d1;  // <--- Warning
+  end
+  assign out = {mem[3], mem[2], mem[1], mem[0]};
 
-   always @(posedge clk) begin
-      out2[7:0] <= d0;  // <--- Warning
-   end
-   always @(negedge clk) begin
-      out2[15:8] <= d0;  // <--- Warning
-   end
+  always @(posedge clk) begin
+    out2[7:0] <= d0;  // <--- Warning
+  end
+  always @(negedge clk) begin
+    out2[15:8] <= d0;  // <--- Warning
+  end
 
 endmodule

test_regress/t/t_while_cond_is_stmt.v

@@ -6,24 +6,26 @@
 
 module t;
 
-    function int unsigned nth_power_of_2(input int unsigned n);
-        nth_power_of_2 = 1;
-        while (n != 0) begin
-            n = n - 1;
-            nth_power_of_2 = nth_power_of_2 << 1;
-        end
-    endfunction
+  function int unsigned nth_power_of_2(input int unsigned n);
+    nth_power_of_2 = 1;
+    while (n != 0) begin
+      n = n - 1;
+      nth_power_of_2 = nth_power_of_2 << 1;
+    end
+  endfunction
 
-    initial begin
-        // Evaluating the function call in the loop condition used
-        // to cause an infinite loop at run-time
-        while (nth_power_of_2(8) != 256) begin
-            $display("2**8 != 256 ?!");
-            $stop;
-        end
-
-        $write("*-* All Finished *-*\n");
-        $finish;
+  initial begin
+    // Evaluating the function call in the loop condition used
+    // to cause an infinite loop at run-time
+    while (nth_power_of_2(
+        8
+    ) != 256) begin
+      $display("2**8 != 256 ?!");
+      $stop;
     end
 
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
 endmodule

test_regress/t/t_while_timing_control.v

@@ -4,21 +4,21 @@
 // SPDX-FileCopyrightText: 2022 Antmicro Ltd
 // SPDX-License-Identifier: CC0-1.0
 
-module t();
-   logic clk = 0;
-   logic out = 1;
+module t;
+  logic clk = 0;
+  logic out = 1;
 
-   always #5 clk = ~clk;
+  always #5 clk = ~clk;
 
-   initial begin
-      while(1) begin
-         if(out) begin
-            break;
-         end
-         @(negedge clk);
+  initial begin
+    while (1) begin
+      if (out) begin
+        break;
       end
+      @(negedge clk);
+    end
 
-      $write("*-* All Finished *-*\n");
-      $finish();
-   end
+    $write("*-* All Finished *-*\n");
+    $finish();
+  end
 endmodule

test_regress/t/t_wide_temp_while_cond.v

@@ -7,20 +7,20 @@
 import "DPI-C" pure function int identity(input int value);
 
 module t;
-   initial begin
-      automatic int n;
-      automatic logic [127:0] val = 128'b1;
-      automatic logic [15:0] one = 16'b1;
+  initial begin
+    automatic int n;
+    automatic logic [127:0] val = 128'b1;
+    automatic logic [15:0] one = 16'b1;
 
-      // This condition involves multiple wide temporaries, and an over-width
-      // shift, all of which requires V3Premit to fix up.
-      while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin
-        ++n;
-      end
+    // This condition involves multiple wide temporaries, and an over-width
+    // shift, all of which requires V3Premit to fix up.
+    while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin
+      ++n;
+    end
 
-      $display("n=%0d", n);
-      if (n != 96) $stop;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+    $display("n=%0d", n);
+    if (n != 96) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule

test_regress/t/t_wire_beh1364_bad.out

@@ -1,22 +1,22 @@
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
                                                : ... note: In instance 't'
-   26 |       w = 0;
-      |       ^
+   26 |     w = 0;
+      |     ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
                                                : ... note: In instance 't'
-   27 |       o = 0;
-      |       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
+   27 |     o = 0;
+      |     ^
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
                                                : ... note: In instance 't'
-   28 |       oa = 0;
-      |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo'
+   28 |     oa = 0;
+      |     ^~
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo'
                                                : ... note: In instance 't'
-   29 |       wo = 0;
-      |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa'
+   29 |     wo = 0;
+      |     ^~
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa'
                                                : ... note: In instance 't'
-   30 |       woa = 0;
-      |       ^~~
+   30 |     woa = 0;
+      |     ^~~
 %Error: Exiting due to

test_regress/t/t_wire_beh1364_bad.v

@@ -4,36 +4,36 @@
 // SPDX-FileCopyrightText: 2018 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
-   // Outputs
-   o, oa, ro, roa, wo, woa
-   );
+module t (  /*AUTOARG*/
+  // Outputs
+  o, oa, ro, roa, wo, woa
+  );
 
-   wire w;
-   reg  r;
-   output o;
-   output [1:0] oa;
-   output reg ro;
-   output reg [1:0] roa;
-   output wire wo;
-   output wire [1:0] woa;
-   //1800 only:
-   //output var vo;
-   //output var [1:0] voa;
+  wire w;
+  reg r;
+  output o;
+  output [1:0] oa;
+  output reg ro;
+  output reg [1:0] roa;
+  output wire wo;
+  output wire [1:0] woa;
+  //1800 only:
+  //output var vo;
+  //output var [1:0] voa;
 
-   initial begin
-      // Error
-      w = 0;
-      o = 0;
-      oa = 0;
-      wo = 0;
-      woa = 0;
-      // Not an error
-      r = 0;
-      ro = 0;
-      roa = 0;
-      //vo = 0;
-      //voa = 0;
-   end
+  initial begin
+    // Error
+    w = 0;
+    o = 0;
+    oa = 0;
+    wo = 0;
+    woa = 0;
+    // Not an error
+    r = 0;
+    ro = 0;
+    roa = 0;
+    //vo = 0;
+    //voa = 0;
+  end
 
 endmodule

test_regress/t/t_wire_beh1800_bad.out

@@ -1,22 +1,22 @@
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
                                                : ... note: In instance 't'
-   25 |       w = '0;   
-      |       ^
+   25 |     w = '0;   
+      |     ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
                                                : ... note: In instance 't'
-   26 |       o = '0;   
-      |       ^
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
+   26 |     o = '0;   
+      |     ^
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
                                                : ... note: In instance 't'
-   27 |       oa = '0;   
-      |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo'
+   27 |     oa = '0;   
+      |     ^~
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo'
                                                : ... note: In instance 't'
-   28 |       wo = '0;   
-      |       ^~
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa'
+   28 |     wo = '0;   
+      |     ^~
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa'
                                                : ... note: In instance 't'
-   29 |       woa = '0;   
-      |       ^~~
+   29 |     woa = '0;   
+      |     ^~~
 %Error: Exiting due to

test_regress/t/t_wire_beh1800_bad.v

@@ -5,33 +5,33 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (/*AUTOARG*/
-   // Outputs
-   o, oa, ro, roa, wo, woa, vo, voa
-   );
+  // Outputs
+  o, oa, ro, roa, wo, woa, vo, voa
+  );
 
-   wire w;
-   reg  r;
-   output o;
-   output [1:0] oa;
-   output reg ro;
-   output reg [1:0] roa;
-   output wire wo;
-   output wire [1:0] woa;
-   // 1800 only
-   output var vo;
-   output var [1:0] voa;
+  wire w;
+  reg  r;
+  output o;
+  output [1:0] oa;
+  output reg ro;
+  output reg [1:0] roa;
+  output wire wo;
+  output wire [1:0] woa;
+  // 1800 only
+  output var vo;
+  output var [1:0] voa;
 
-   initial begin
-      w = '0;  // Error
-      o = '0;  // Error
-      oa = '0;  // Error
-      wo = '0;  // Error
-      woa = '0;  // Error
-      r = '0;  // Not an error
-      ro = '0;  // Not an error
-      roa = '0;  // Not an error
-      vo = '0;  // Not an error
-      voa = '0;  // Not an error
-   end
+  initial begin
+    w = '0;  // Error
+    o = '0;  // Error
+    oa = '0;  // Error
+    wo = '0;  // Error
+    woa = '0;  // Error
+    r = '0;  // Not an error
+    ro = '0;  // Not an error
+    roa = '0;  // Not an error
+    vo = '0;  // Not an error
+    voa = '0;  // Not an error
+  end
 
 endmodule

test_regress/t/t_wire_behp1364_bad.out

@@ -1,14 +1,14 @@
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
                                                 : ... note: In instance 't'
-   24 |       w = 0;
-      |       ^
+   24 |     w = 0;
+      |     ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
                                                 : ... note: In instance 't'
-   25 |       o = 0;
-      |       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
+   25 |     o = 0;
+      |     ^
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
                                                 : ... note: In instance 't'
-   26 |       oa = 0;
-      |       ^~
+   26 |     oa = 0;
+      |     ^~
 %Error: Exiting due to

test_regress/t/t_wire_behp1364_bad.v

@@ -5,33 +5,33 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-   output o,
-   output [1:0] oa,
-   output reg ro,
-   output reg [1:0] roa,
-   output wire wo,
-   output wire [1:0] woa
-   //1800 only:
-   //output var vo;
-   //output var [1:0] voa;
-   );
+    output o,
+    output [1:0] oa,
+    output reg ro,
+    output reg [1:0] roa,
+    output wire wo,
+    output wire [1:0] woa
+    //1800 only:
+    //output var vo;
+    //output var [1:0] voa;
+);
 
-   wire w;
-   reg  r;
+  wire w;
+  reg r;
 
-   initial begin
-      // Error
-      w = 0;
-      o = 0;
-      oa = 0;
-      wo = 0;
-      woa = 0;
-      // Not an error
-      r = 0;
-      ro = 0;
-      roa = 0;
-      //vo = 0;
-      //voa = 0;
-   end
+  initial begin
+    // Error
+    w = 0;
+    o = 0;
+    oa = 0;
+    wo = 0;
+    woa = 0;
+    // Not an error
+    r = 0;
+    ro = 0;
+    roa = 0;
+    //vo = 0;
+    //voa = 0;
+  end
 
 endmodule

test_regress/t/t_wire_behp1800_bad.out

@@ -1,14 +1,14 @@
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w'
                                                 : ... note: In instance 't'
-   23 |       w = '0;   
-      |       ^
+   23 |     w = '0;   
+      |     ^
                     ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o'
                                                 : ... note: In instance 't'
-   24 |       o = '0;   
-      |       ^
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
+   24 |     o = '0;   
+      |     ^
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa'
                                                 : ... note: In instance 't'
-   25 |       oa = '0;   
-      |       ^~
+   25 |     oa = '0;   
+      |     ^~
 %Error: Exiting due to

test_regress/t/t_wire_behp1800_bad.v

@@ -5,31 +5,31 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-   output o,
-   output [1:0] oa,
-   output reg ro,
-   output reg [1:0] roa,
-   output wire wo,
-   output wire [1:0] woa,
-   // 1800 only
-   output var vo,
-   output var [1:0] voa
-   );
+    output o,
+    output [1:0] oa,
+    output reg ro,
+    output reg [1:0] roa,
+    output wire wo,
+    output wire [1:0] woa,
+    // 1800 only
+    output var vo,
+    output var [1:0] voa
+);
 
-   wire w;
-   reg  r;
+  wire w;
+  reg r;
 
-   initial begin
-      w = '0;  // Error
-      o = '0;  // Error
-      oa = '0;  // Error
-      wo = '0;  // Error
-      woa = '0;  // Error
-      r = '0;  // Not an error
-      ro = '0;  // Not an error
-      roa = '0;  // Not an error
-      vo = '0;  // Not an error
-      voa = '0;  // Not an error
-   end
+  initial begin
+    w = '0;  // Error
+    o = '0;  // Error
+    oa = '0;  // Error
+    wo = '0;  // Error
+    woa = '0;  // Error
+    r = '0;  // Not an error
+    ro = '0;  // Not an error
+    roa = '0;  // Not an error
+    vo = '0;  // Not an error
+    voa = '0;  // Not an error
+  end
 
 endmodule

test_regress/t/t_wire_self_bad.out

@@ -1,5 +1,5 @@
-%Error: t/t_wire_self_bad.v:11:16: Wire inputs its own output, creating circular logic (wire x=x)
-   11 |    wire myself = myself;
-      |                ^
+%Error: t/t_wire_self_bad.v:11:15: Wire inputs its own output, creating circular logic (wire x=x)
+   11 |   wire myself = myself;
+      |               ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_wire_self_bad.v

@@ -8,6 +8,6 @@
 
 module t;
 
-   wire myself = myself;
+  wire myself = myself;
 
 endmodule

test_regress/t/t_wire_types.v

@@ -4,35 +4,37 @@
 // SPDX-FileCopyrightText: 2012 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
+  // Inputs
+  clk
+  );
+  input clk;
 
-   // IEEE: integer_atom_type
-   wire integer w_integer;
+  // IEEE: integer_atom_type
+  wire integer w_integer;
 
-   // IEEE: integer_atom_type
-   wire logic   w_logic;
+  // IEEE: integer_atom_type
+  wire logic  w_logic;
 
-   wire logic  [1:0]    w_logic2;
+  wire logic  [1:0]   w_logic2;
 
-   assign w_integer = -123456;
+  assign w_integer = -123456;
 
-   assign w_logic = 1'b1;
+  assign w_logic = 1'b1;
 
-   assign w_logic2 = 2'b10;
+  assign w_logic2 = 2'b10;
 
-   always @ (posedge clk) begin
-      `checkh(w_integer, -123456);
-      `checkh(w_logic, 1'b1);
-      `checkh(w_logic2, 2'b10);
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  always @ (posedge clk) begin
+    `checkh(w_integer, -123456);
+    `checkh(w_logic, 1'b1);
+    `checkh(w_logic2, 2'b10);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule

test_regress/t/t_wired_net_test.v

@@ -4,68 +4,70 @@
 // SPDX-FileCopyrightText: 2022 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t(
 clk
 /*AUTOARG*/);
-   input clk;
-   wor [3:0] ptrior1;
-   trior [3:0] ptrior2;
-   wand [3:0] ptriand1;
-   triand [3:0] ptriand2;
-   wire [3:0] z1;
-   wire [3:0] z2;
-   wire [3:0] tri_z1;
-   wire [3:0] tri_z2;
-   logic [3:0] x;
-   logic [3:0] y;
-   logic [3:0] tri_x;
-   logic [3:0] tri_y;
-   logic [3:0] tri_x_dat;
-   logic [3:0] tri_y_dat;
-   logic [3:0] tri_x_en;
-   logic [3:0] tri_y_en;
-   assign ptrior1 = x & y;
-   assign ptrior1 = x + y;
-   assign ptrior2 = tri_x & tri_y;
-   assign ptrior2 = tri_x + tri_y;
-   assign ptriand1 = x & y;
-   assign ptriand1 = x + y;
-   assign ptriand2 = tri_x & tri_y;
-   assign ptriand2 = tri_x + tri_y;
-   assign z1 = (x & y) | (x + y);
-   assign z2 = (x & y) & (x + y);
-   assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y);
-   assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y);
-   integer cyc = 0;
-   integer xz_index = 0;
-   integer xz_num = 0;
-   integer i;
-   assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz;
-   assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz;
-   assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz;
-   assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz;
-   assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz;
-   assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz;
-   assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz;
-   assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz;
-   always @ (posedge clk) begin
-      cyc <= cyc + 1;
-      x = {$random}[3:0];
-      y = {$random}[3:0];
-      tri_x_dat = {$random}[3:0];
-      tri_y_dat = {$random}[3:0];
-      tri_x_en = {$random}[3:0];
-      tri_y_en = {$random}[3:0];
-      `checkb(ptrior1, z1);
-      `checkb(ptrior2, tri_z1);
-      `checkb(ptriand1, z2);
-      `checkb(ptriand2, tri_z2);
-      if (cyc == 20) begin
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
+  input clk;
+  wor [3:0] ptrior1;
+  trior [3:0] ptrior2;
+  wand [3:0] ptriand1;
+  triand [3:0] ptriand2;
+  wire [3:0] z1;
+  wire [3:0] z2;
+  wire [3:0] tri_z1;
+  wire [3:0] tri_z2;
+  logic [3:0] x;
+  logic [3:0] y;
+  logic [3:0] tri_x;
+  logic [3:0] tri_y;
+  logic [3:0] tri_x_dat;
+  logic [3:0] tri_y_dat;
+  logic [3:0] tri_x_en;
+  logic [3:0] tri_y_en;
+  assign ptrior1 = x & y;
+  assign ptrior1 = x + y;
+  assign ptrior2 = tri_x & tri_y;
+  assign ptrior2 = tri_x + tri_y;
+  assign ptriand1 = x & y;
+  assign ptriand1 = x + y;
+  assign ptriand2 = tri_x & tri_y;
+  assign ptriand2 = tri_x + tri_y;
+  assign z1 = (x & y) | (x + y);
+  assign z2 = (x & y) & (x + y);
+  assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y);
+  assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y);
+  integer cyc = 0;
+  integer xz_index = 0;
+  integer xz_num = 0;
+  integer i;
+  assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz;
+  assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz;
+  assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz;
+  assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz;
+  assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz;
+  assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz;
+  assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz;
+  assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz;
+  always @ (posedge clk) begin
+    cyc <= cyc + 1;
+    x = {$random}[3:0];
+    y = {$random}[3:0];
+    tri_x_dat = {$random}[3:0];
+    tri_y_dat = {$random}[3:0];
+    tri_x_en = {$random}[3:0];
+    tri_y_en = {$random}[3:0];
+    `checkb(ptrior1, z1);
+    `checkb(ptrior2, tri_z1);
+    `checkb(ptriand1, z2);
+    `checkb(ptriand2, tri_z2);
+    if (cyc == 20) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
 endmodule

test_regress/t/t_with_suggest_bad.out

@@ -1,10 +1,10 @@
-%Error: t/t_with_suggest_bad.v:16:25: Can't find definition of variable: 'itemm'
+%Error: t/t_with_suggest_bad.v:16:23: Can't find definition of variable: 'itemm'
                                     : ... Suggested alternative: 'item'
-   16 |       qv = q.find with (itemm == 2);
-      |                         ^~~~~
+   16 |     qv = q.find with (itemm == 2);
+      |                       ^~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_with_suggest_bad.v:18:37: Can't find definition of variable: 'misspelledd'
+%Error: t/t_with_suggest_bad.v:18:35: Can't find definition of variable: 'misspelledd'
                                     : ... Suggested alternative: 'misspelled'
-   18 |       qv = q.find(misspelled) with (misspelledd == 2);
-      |                                     ^~~~~~~~~~~
+   18 |     qv = q.find(misspelled) with (misspelledd == 2);
+      |                                   ^~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_with_suggest_bad.v

@@ -8,14 +8,14 @@
 
 module t;
 
-   initial begin
-      int q[$];
-      int qv[$];  // Value returns
-      q = '{1, 2, 2, 4, 3};
+  initial begin
+    int q[$];
+    int qv[$];  // Value returns
+    q = '{1, 2, 2, 4, 3};
 
-      qv = q.find with (itemm == 2);
+    qv = q.find with (itemm == 2);
 
-      qv = q.find(misspelled) with (misspelledd == 2);
-   end
+    qv = q.find(misspelled) with (misspelledd == 2);
+  end
 
 endmodule

test_regress/t/t_wrapper_clone.v

@@ -7,32 +7,32 @@
 // SPDX-FileCopyrightText: 2023 Yinan Xu
 // SPDX-License-Identifier: CC0-1.0
 
-module top(
-  input clock,
-  input reset,
-  input is_parent,
-  output do_clone
+module top (
+    input clock,
+    input reset,
+    input is_parent,
+    output do_clone
 );
 
-reg [3:0] counter;
+  reg [3:0] counter;
 
-assign do_clone = counter == 4'h6;
+  assign do_clone = counter == 4'h6;
 
-always @(posedge clock) begin
-  if (reset) begin
-    counter <= 4'h0;
-  end
-  else begin
-    counter <= counter + 4'h1;
-    $write("counter = %d\n", counter);
-  end
-
-  if (counter[3]) begin
-    if (is_parent) begin
-      $write("*-* All Finished *-*\n");
+  always @(posedge clock) begin
+    if (reset) begin
+      counter <= 4'h0;
+    end
+    else begin
+      counter <= counter + 4'h1;
+      $write("counter = %d\n", counter);
+    end
+
+    if (counter[3]) begin
+      if (is_parent) begin
+        $write("*-* All Finished *-*\n");
+      end
+      $finish(0);
     end
-    $finish(0);
   end
-end
 
 endmodule

test_regress/t/t_wrapper_context.v

@@ -9,50 +9,47 @@
 
 `define STRINGIFY(x) `"x`"
 
-module top
-  (
-   input             clk,
-   input             rst,
-   input [31:0]      trace_number,
-   input             stop,
-   output bit [31:0] counter,
-   output bit        done_o
-   );
+module top (
+    input clk,
+    input rst,
+    input [31:0] trace_number,
+    input stop,
+    output bit [31:0] counter,
+    output bit done_o
+);
 
-   initial begin
-      string number;
-      string filename;
-      number.itoa(trace_number);
+  initial begin
+    string number;
+    string filename;
+    number.itoa(trace_number);
 `ifdef TRACE_FST
-      filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".fst"};
+    filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".fst"};
 `else
-      filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"};
+    filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"};
 `endif
-      $display("Writing dumpfile '%s'", filename);
-      $dumpfile(filename);
-      $dumpvars();
-   end
+    $display("Writing dumpfile '%s'", filename);
+    $dumpfile(filename);
+    $dumpvars();
+  end
 
-   always@(posedge clk) begin
-      if (rst)
-        counter <= 0;
-      else
-        counter <= counter + 1;
-   end
-   always_comb begin
-      done_o = '0;
-      if (stop) begin
-         if (counter >= 5 && stop) begin
-            done_o = '1;
-            $stop;
-         end
+  always @(posedge clk) begin
+    if (rst) counter <= 0;
+    else counter <= counter + 1;
+  end
+  always_comb begin
+    done_o = '0;
+    if (stop) begin
+      if (counter >= 5 && stop) begin
+        done_o = '1;
+        $stop;
       end
-      else begin
-         if (counter >= 10) begin
-            done_o = '1;
-            $finish;
-         end
+    end
+    else begin
+      if (counter >= 10) begin
+        done_o = '1;
+        $finish;
       end
-   end
+    end
+  end
 
 endmodule

test_regress/t/t_wrapper_context__top0.dat.out

@@ -1,150 +1,150 @@
 # SystemC::Coverage-3
-C '
ft/t_wrapper_context.v
l14
n22
ttoggle
pagev_toggle/top
oclk:0->1
htop0.top' 11
-C '
ft/t_wrapper_context.v
l14
n22
ttoggle
pagev_toggle/top
oclk:1->0
htop0.top' 10
-C '
ft/t_wrapper_context.v
l15
n22
ttoggle
pagev_toggle/top
orst:0->1
htop0.top' 1
-C '
ft/t_wrapper_context.v
l15
n22
ttoggle
pagev_toggle/top
orst:1->0
htop0.top' 1
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[0]:0->1
htop0.top' 1
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[0]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[10]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[10]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[11]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[11]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[12]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[12]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[13]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[13]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[14]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[14]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[15]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[15]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[16]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[16]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[17]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[17]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[18]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
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htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[19]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[19]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[1]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[20]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[20]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[21]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[21]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[22]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[22]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[23]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[23]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[24]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[24]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
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ttoggle
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otrace_number[25]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
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ttoggle
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otrace_number[25]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
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otrace_number[26]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
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otrace_number[26]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[27]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[27]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[28]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[28]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[29]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[29]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[2]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[2]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[30]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[30]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[31]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[31]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[3]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[3]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[4]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[4]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[5]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[5]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[6]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[6]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[7]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[7]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[8]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[8]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[9]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[9]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l17
n22
ttoggle
pagev_toggle/top
ostop:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l17
n22
ttoggle
pagev_toggle/top
ostop:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[0]:0->1
htop0.top' 5
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[0]:1->0
htop0.top' 5
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[10]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[10]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[11]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[11]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[12]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[12]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[13]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[13]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[14]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[14]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[15]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[15]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[16]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[16]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[17]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[17]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[18]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[18]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[19]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[19]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[1]:0->1
htop0.top' 3
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[1]:1->0
htop0.top' 2
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[20]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[20]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[21]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[21]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[22]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[22]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[23]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[23]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[24]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[24]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[25]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[25]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[26]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[26]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[27]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[27]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[28]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[28]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[29]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[29]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[2]:0->1
htop0.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[2]:1->0
htop0.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[30]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[30]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[31]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[31]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[3]:0->1
htop0.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[3]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[4]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[4]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[5]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[5]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[6]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[6]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[7]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[7]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[8]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[8]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[9]:0->1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[9]:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l19
n22
ttoggle
pagev_toggle/top
odone_o:0->1
htop0.top' 1
-C '
ft/t_wrapper_context.v
l19
n22
ttoggle
pagev_toggle/top
odone_o:1->0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l22
n4
tline
pagev_line/top
oblock
S22,25,29,31-33
htop0.top' 1
-C '
ft/t_wrapper_context.v
l36
n4
tline
pagev_line/top
oblock
S36
htop0.top' 11
-C '
ft/t_wrapper_context.v
l37
n7
tbranch
pagev_branch/top
oif
S37-38
htop0.top' 1
-C '
ft/t_wrapper_context.v
l37
n8
tbranch
pagev_branch/top
oelse
S40
htop0.top' 10
-C '
ft/t_wrapper_context.v
l42
n4
tline
pagev_line/top
oblock
S42-43
htop0.top' 34
-C '
ft/t_wrapper_context.v
l44
n7
tbranch
pagev_branch/top
oif
S44
htop0.top' 0
-C '
ft/t_wrapper_context.v
l44
n8
tbranch
pagev_branch/top
oelse
S50
htop0.top' 34
-C '
ft/t_wrapper_context.v
l45
n11
tline
pagev_line/top
oelse
htop0.top' 0
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o((counter >= 32'sh5)==0) => 0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o((counter >= 32'sh5)==1 && stop==1) => 1
htop0.top' 0
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o(stop==0) => 0
htop0.top' 0
-C '
ft/t_wrapper_context.v
l51
n10
tbranch
pagev_branch/top
oif
S51-53
htop0.top' 1
-C '
ft/t_wrapper_context.v
l51
n11
tbranch
pagev_branch/top
oelse
htop0.top' 33
+C '
ft/t_wrapper_context.v
l13
n11
ttoggle
pagev_toggle/top
oclk:0->1
htop0.top' 11
+C '
ft/t_wrapper_context.v
l13
n11
ttoggle
pagev_toggle/top
oclk:1->0
htop0.top' 10
+C '
ft/t_wrapper_context.v
l14
n11
ttoggle
pagev_toggle/top
orst:0->1
htop0.top' 1
+C '
ft/t_wrapper_context.v
l14
n11
ttoggle
pagev_toggle/top
orst:1->0
htop0.top' 1
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[0]:0->1
htop0.top' 1
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[0]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[10]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[10]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[11]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[11]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[12]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[12]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[13]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[13]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[14]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[14]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[15]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[15]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[16]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[16]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[17]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[17]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[18]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[18]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[19]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[19]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[1]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[1]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[20]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[20]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[21]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[21]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[22]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[22]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[23]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[23]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[24]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[24]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[25]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[25]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[26]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[26]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[27]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[27]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[28]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[28]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[29]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[29]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[2]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[2]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[30]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[30]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[31]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[31]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[3]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[3]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[4]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[4]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[5]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[5]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[6]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[6]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[7]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[7]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[8]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[8]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[9]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[9]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l16
n11
ttoggle
pagev_toggle/top
ostop:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l16
n11
ttoggle
pagev_toggle/top
ostop:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[0]:0->1
htop0.top' 5
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[0]:1->0
htop0.top' 5
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[10]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[10]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[11]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[11]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[12]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[12]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[13]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[13]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[14]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[14]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[15]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[15]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[16]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[16]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[17]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[17]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[18]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[18]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[19]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[19]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[1]:0->1
htop0.top' 3
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[1]:1->0
htop0.top' 2
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[20]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[20]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[21]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[21]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[22]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[22]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[23]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[23]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[24]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[24]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[25]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[25]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[26]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[26]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[27]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[27]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[28]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[28]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[29]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[29]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[2]:0->1
htop0.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[2]:1->0
htop0.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[30]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[30]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[31]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[31]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[3]:0->1
htop0.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[3]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[4]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[4]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[5]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[5]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[6]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[6]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[7]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[7]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[8]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[8]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[9]:0->1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[9]:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l18
n16
ttoggle
pagev_toggle/top
odone_o:0->1
htop0.top' 1
+C '
ft/t_wrapper_context.v
l18
n16
ttoggle
pagev_toggle/top
odone_o:1->0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l21
n3
tline
pagev_line/top
oblock
S21,24,28,30-32
htop0.top' 1
+C '
ft/t_wrapper_context.v
l35
n3
tline
pagev_line/top
oblock
S35
htop0.top' 11
+C '
ft/t_wrapper_context.v
l36
n5
tbranch
pagev_branch/top
oif
S36
htop0.top' 1
+C '
ft/t_wrapper_context.v
l36
n6
tbranch
pagev_branch/top
oelse
S37
htop0.top' 10
+C '
ft/t_wrapper_context.v
l39
n3
tline
pagev_line/top
oblock
S39-40
htop0.top' 34
+C '
ft/t_wrapper_context.v
l41
n5
tbranch
pagev_branch/top
oif
S41
htop0.top' 0
+C '
ft/t_wrapper_context.v
l41
n6
tbranch
pagev_branch/top
oelse
S47
htop0.top' 34
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o((counter >= 32'sh5)==0) => 0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o((counter >= 32'sh5)==1 && stop==1) => 1
htop0.top' 0
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o(stop==0) => 0
htop0.top' 0
+C '
ft/t_wrapper_context.v
l42
n8
tline
pagev_line/top
oelse
htop0.top' 0
+C '
ft/t_wrapper_context.v
l48
n7
tbranch
pagev_branch/top
oif
S48-50
htop0.top' 1
+C '
ft/t_wrapper_context.v
l48
n8
tbranch
pagev_branch/top
oelse
htop0.top' 33

test_regress/t/t_wrapper_context__top1.dat.out

@@ -1,150 +1,150 @@
 # SystemC::Coverage-3
-C '
ft/t_wrapper_context.v
l14
n22
ttoggle
pagev_toggle/top
oclk:0->1
htop1.top' 6
-C '
ft/t_wrapper_context.v
l14
n22
ttoggle
pagev_toggle/top
oclk:1->0
htop1.top' 5
-C '
ft/t_wrapper_context.v
l15
n22
ttoggle
pagev_toggle/top
orst:0->1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l15
n22
ttoggle
pagev_toggle/top
orst:1->0
htop1.top' 1
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[0]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[0]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[10]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[10]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[11]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[11]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[12]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[12]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[13]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[13]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[14]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[14]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[15]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[15]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[16]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[16]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[17]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[17]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[18]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[18]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[19]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[19]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[1]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[1]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[20]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[20]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[21]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[21]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[22]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[22]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[23]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[23]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[24]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[24]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[25]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[25]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[26]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[26]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[27]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[27]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[28]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[28]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[29]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[29]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[2]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[2]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[30]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[30]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[31]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[31]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[3]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[3]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[4]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[4]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[5]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[5]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[6]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[6]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[7]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[7]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[8]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[8]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[9]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l16
n22
ttoggle
pagev_toggle/top
otrace_number[9]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l17
n22
ttoggle
pagev_toggle/top
ostop:0->1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l17
n22
ttoggle
pagev_toggle/top
ostop:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[0]:0->1
htop1.top' 3
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[0]:1->0
htop1.top' 2
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[10]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[10]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[11]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[11]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[12]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[12]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[13]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[13]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[14]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[14]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[15]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[15]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[16]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[16]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[17]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[17]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[18]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[18]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[19]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[19]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[1]:0->1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[1]:1->0
htop1.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[20]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[20]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[21]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[21]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[22]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[22]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[23]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[23]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[24]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[24]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[25]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[25]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[26]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[26]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[27]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[27]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[28]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[28]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[29]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[29]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[2]:0->1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[2]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[30]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[30]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[31]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[31]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[3]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[3]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[4]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[4]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[5]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[5]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[6]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[6]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[7]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[7]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[8]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[8]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[9]:0->1
htop1.top' 0
-C '
ft/t_wrapper_context.v
l18
n22
ttoggle
pagev_toggle/top
ocounter[9]:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l19
n22
ttoggle
pagev_toggle/top
odone_o:0->1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l19
n22
ttoggle
pagev_toggle/top
odone_o:1->0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l22
n4
tline
pagev_line/top
oblock
S22,25,29,31-33
htop1.top' 1
-C '
ft/t_wrapper_context.v
l36
n4
tline
pagev_line/top
oblock
S36
htop1.top' 6
-C '
ft/t_wrapper_context.v
l37
n7
tbranch
pagev_branch/top
oif
S37-38
htop1.top' 1
-C '
ft/t_wrapper_context.v
l37
n8
tbranch
pagev_branch/top
oelse
S40
htop1.top' 5
-C '
ft/t_wrapper_context.v
l42
n4
tline
pagev_line/top
oblock
S42-43
htop1.top' 19
-C '
ft/t_wrapper_context.v
l44
n7
tbranch
pagev_branch/top
oif
S44
htop1.top' 19
-C '
ft/t_wrapper_context.v
l44
n8
tbranch
pagev_branch/top
oelse
S50
htop1.top' 0
-C '
ft/t_wrapper_context.v
l45
n11
tline
pagev_line/top
oelse
htop1.top' 18
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o((counter >= 32'sh5)==0) => 0
htop1.top' 18
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o((counter >= 32'sh5)==1 && stop==1) => 1
htop1.top' 1
-C '
ft/t_wrapper_context.v
l45
n27
texpr
pagev_expr/top
o(stop==0) => 0
htop1.top' 0
-C '
ft/t_wrapper_context.v
l51
n10
tbranch
pagev_branch/top
oif
S51-53
htop1.top' 0
-C '
ft/t_wrapper_context.v
l51
n11
tbranch
pagev_branch/top
oelse
htop1.top' 0
+C '
ft/t_wrapper_context.v
l13
n11
ttoggle
pagev_toggle/top
oclk:0->1
htop1.top' 6
+C '
ft/t_wrapper_context.v
l13
n11
ttoggle
pagev_toggle/top
oclk:1->0
htop1.top' 5
+C '
ft/t_wrapper_context.v
l14
n11
ttoggle
pagev_toggle/top
orst:0->1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l14
n11
ttoggle
pagev_toggle/top
orst:1->0
htop1.top' 1
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[0]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[0]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[10]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[10]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[11]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[11]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[12]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[12]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[13]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[13]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[14]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[14]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[15]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[15]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[16]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[16]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[17]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[17]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[18]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[18]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[19]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[19]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[1]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[1]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[20]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[20]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[21]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[21]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[22]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[22]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[23]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[23]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[24]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[24]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[25]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[25]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[26]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[26]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[27]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[27]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[28]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[28]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[29]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[29]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[2]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[2]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[30]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[30]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[31]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[31]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[3]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[3]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[4]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[4]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[5]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[5]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[6]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[6]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[7]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[7]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[8]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[8]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[9]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l15
n18
ttoggle
pagev_toggle/top
otrace_number[9]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l16
n11
ttoggle
pagev_toggle/top
ostop:0->1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l16
n11
ttoggle
pagev_toggle/top
ostop:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[0]:0->1
htop1.top' 3
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[0]:1->0
htop1.top' 2
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[10]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[10]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[11]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[11]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[12]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[12]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[13]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[13]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[14]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[14]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[15]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[15]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[16]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[16]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[17]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[17]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[18]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[18]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[19]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[19]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[1]:0->1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[1]:1->0
htop1.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[20]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[20]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[21]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[21]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[22]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[22]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[23]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[23]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[24]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[24]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[25]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[25]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[26]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[26]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[27]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[27]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[28]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[28]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[29]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[29]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[2]:0->1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[2]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[30]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[30]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[31]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[31]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[3]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[3]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[4]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[4]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[5]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[5]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[6]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[6]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[7]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[7]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[8]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[8]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[9]:0->1
htop1.top' 0
+C '
ft/t_wrapper_context.v
l17
n23
ttoggle
pagev_toggle/top
ocounter[9]:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l18
n16
ttoggle
pagev_toggle/top
odone_o:0->1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l18
n16
ttoggle
pagev_toggle/top
odone_o:1->0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l21
n3
tline
pagev_line/top
oblock
S21,24,28,30-32
htop1.top' 1
+C '
ft/t_wrapper_context.v
l35
n3
tline
pagev_line/top
oblock
S35
htop1.top' 6
+C '
ft/t_wrapper_context.v
l36
n5
tbranch
pagev_branch/top
oif
S36
htop1.top' 1
+C '
ft/t_wrapper_context.v
l36
n6
tbranch
pagev_branch/top
oelse
S37
htop1.top' 5
+C '
ft/t_wrapper_context.v
l39
n3
tline
pagev_line/top
oblock
S39-40
htop1.top' 19
+C '
ft/t_wrapper_context.v
l41
n5
tbranch
pagev_branch/top
oif
S41
htop1.top' 19
+C '
ft/t_wrapper_context.v
l41
n6
tbranch
pagev_branch/top
oelse
S47
htop1.top' 0
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o((counter >= 32'sh5)==0) => 0
htop1.top' 18
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o((counter >= 32'sh5)==1 && stop==1) => 1
htop1.top' 1
+C '
ft/t_wrapper_context.v
l42
n24
texpr
pagev_expr/top
o(stop==0) => 0
htop1.top' 0
+C '
ft/t_wrapper_context.v
l42
n8
tline
pagev_line/top
oelse
htop1.top' 18
+C '
ft/t_wrapper_context.v
l48
n7
tbranch
pagev_branch/top
oif
S48-50
htop1.top' 0
+C '
ft/t_wrapper_context.v
l48
n8
tbranch
pagev_branch/top
oelse
htop1.top' 0

test_regress/t/t_wrapper_del_context_bad.v

@@ -5,5 +5,5 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module top;
-   initial $finish;
+  initial $finish;
 endmodule

test_regress/t/t_wrapper_legacy.v

@@ -5,20 +5,20 @@
 // SPDX-License-Identifier: CC0-1.0
 
 
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
+module t (  /*AUTOARG*/
+    // Inputs
+    clk
+);
 
-   input clk;
-   int   count;
+  input clk;
+  int count;
 
-   always @(posedge clk) begin
-      count <= count + 1;
-      if (count == 10) begin
-        $write("*-* All Finished *-*\n");
-        $finish;
-      end
-   end
+  always @(posedge clk) begin
+    count <= count + 1;
+    if (count == 10) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
 
 endmodule : t

test_regress/t/t_wrapper_reuse_context_bad.v

@@ -5,5 +5,5 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module top;
-   initial $finish;
+  initial $finish;
 endmodule

test_regress/t/t_x_assign.v

@@ -6,13 +6,14 @@
 // SPDX-FileCopyrightText: 2020 Geza Lore
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-module t_x_assign(
-   input wire clk,
-   output reg o,
-   output reg[31:0] o_int
+module t_x_assign (
+    input wire clk,
+    output reg o,
+    output reg [31:0] o_int
 );
-   always @(posedge clk) begin
-      if (1'bx) o <= 1'd1; else o <= 1'd0;
-      o_int <= 'x;
-   end
+  always @(posedge clk) begin
+    if (1'bx) o <= 1'd1;
+    else o <= 1'd0;
+    o_int <= 'x;
+  end
 endmodule

test_regress/t/t_x_rand_stability.v

@@ -9,66 +9,66 @@ module t (
     input clk
 );
 
-    int cyc = 0;
+  int cyc = 0;
 
-    logic [31:0] uninitialized;
-    logic [31:0] x_assigned = '0;
+  logic [31:0] uninitialized;
+  logic [31:0] x_assigned = '0;
 `ifdef ADD_SIGNAL
-    logic [31:0] added;
-    logic [31:0] x_assigned_added = '0;
+  logic [31:0] added;
+  logic [31:0] x_assigned_added = '0;
 `endif
-    logic [31:0] unused;
-    logic [31:0] x_assigned_unused = '0;
-    logic [31:0] uninitialized2;
-    logic [255:0] big;
-    int random_init = $random();
+  logic [31:0] unused;
+  logic [31:0] x_assigned_unused = '0;
+  logic [31:0] uninitialized2;
+  logic [255:0] big;
+  int random_init = $random();
 
-    sub_no_inline the_sub_no_inline_1();
-    sub_no_inline the_sub_no_inline_2();
-    sub_yes_inline the_sub_yes_inline_1();
-    sub_yes_inline the_sub_yes_inline_2();
+  sub_no_inline the_sub_no_inline_1 ();
+  sub_no_inline the_sub_no_inline_2 ();
+  sub_yes_inline the_sub_yes_inline_1 ();
+  sub_yes_inline the_sub_yes_inline_2 ();
 
-    initial begin
-        $display("uninitialized = 0x%x", uninitialized);
-        $display("x_assigned (initial) = 0x%x", x_assigned);
-        $display("uninitialized2 = 0x%x", uninitialized2);
-        $display("big = 0x%x", big);
-        $display("random_init = 0x%x", random_init);
-    end
+  initial begin
+    $display("uninitialized = 0x%x", uninitialized);
+    $display("x_assigned (initial) = 0x%x", x_assigned);
+    $display("uninitialized2 = 0x%x", uninitialized2);
+    $display("big = 0x%x", big);
+    $display("random_init = 0x%x", random_init);
+  end
 
-    always @(posedge clk) begin
-        x_assigned_unused = 'x;
-        x_assigned <= 'x;
+  always @(posedge clk) begin
+    x_assigned_unused = 'x;
+    x_assigned <= 'x;
 `ifdef ADD_SIGNAL
-        x_assigned_added <= 'x;
+    x_assigned_added <= 'x;
 `endif
-        cyc <= cyc + 1;
-        $display("rand = 0x%x", $random());
-        if (cyc == 4) begin
-            $display("x_assigned = 0x%x", x_assigned);
+    cyc <= cyc + 1;
+    $display("rand = 0x%x", $random());
+    if (cyc == 4) begin
+      $display("x_assigned = 0x%x", x_assigned);
 `ifndef NOT_RAND
-            if (uninitialized == uninitialized2) $stop();
-            if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop();
-            if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop();
+      if (uninitialized == uninitialized2) $stop();
+      if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop();
+      if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop();
 `endif
 `ifdef ADD_SIGNAL
-            if (added == 0) $stop();
-            if (x_assigned_added == 0) $stop();
+      if (added == 0) $stop();
+      if (x_assigned_added == 0) $stop();
 `endif
-            $display("Last rand = 0x%x", $random());
-            $write("*-* All Finished *-*\n");
-            $finish;
-        end
+      $display("Last rand = 0x%x", $random());
+      $write("*-* All Finished *-*\n");
+      $finish;
     end
+  end
 
 endmodule
 
-module sub_no_inline; /* verilator no_inline_module */
-    logic [63:0] no_init;
-    initial $display("%m no_init 0x%0x", no_init);
+module sub_no_inline;  /* verilator no_inline_module */
+  logic [63:0] no_init;
+  initial $display("%m no_init 0x%0x", no_init);
 endmodule
 
-module sub_yes_inline; /* verilator inline_module */
-    logic [63:0] no_init;
-    initial $display("%m no_init 0x%0x", no_init);
+module sub_yes_inline;  /* verilator inline_module */
+  logic [63:0] no_init;
+  initial $display("%m no_init 0x%0x", no_init);
 endmodule