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@ -3135,6 +3135,24 @@ class RandomizeVisitor final : public VNVisitor {
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}
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};
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// Wrap obj.randomize() with null guard: (obj != null) ? obj.randomize() : 0
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// IEEE 1800 requires randomize() on null handle to return 0.
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// Uses user4() to prevent re-wrapping during iterateChildren.
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void wrapRandomizeCallWithNullGuard(AstNodeFTaskRef* nodep) {
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AstMethodCall* const callp = VN_CAST(nodep, MethodCall);
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if (!callp) return;
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if (callp->user4()) return;
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callp->user4(true);
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FileLine* const fl = callp->fileline();
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AstNodeExpr* const checkp
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= new AstNeq{fl, callp->fromp()->cloneTree(false), new AstConst{fl, AstConst::Null{}}};
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VNRelinker relinker;
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callp->unlinkFrBack(&relinker);
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AstCond* const condp = new AstCond{fl, checkp, callp, new AstConst{fl, 0}};
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condp->dtypeFrom(callp);
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relinker.relink(condp);
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}
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// Handle inline random variable control. After this, the randomize() call has no args
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void handleRandomizeArgs(AstNodeFTaskRef* const nodep) {
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if (!nodep->pinsp()) return;
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@ -3593,6 +3611,7 @@ class RandomizeVisitor final : public VNVisitor {
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AstWith* const withp = VN_CAST(nodep->pinsp(), With);
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if (!withp) {
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iterateChildren(nodep);
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wrapRandomizeCallWithNullGuard(nodep);
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return;
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}
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withp->unlinkFrBack();
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@ -3730,6 +3749,7 @@ class RandomizeVisitor final : public VNVisitor {
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nodep->dtypeFrom(randomizeFuncp->dtypep());
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nodep->classOrPackagep(classp);
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UINFO(9, "Added `%s` randomization procedure");
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wrapRandomizeCallWithNullGuard(nodep);
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VL_DO_DANGLING(withp->deleteTree(), withp);
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}
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void visit(AstConstraint* nodep) override {
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,37 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
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// verilog_format: on
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class SimpleRandClass;
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rand bit [7:0] value;
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constraint value_con { value > 0 && value < 200; }
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function new();
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endfunction
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endclass
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module t;
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SimpleRandClass obj;
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int rand_result;
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initial begin
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obj = null;
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rand_result = obj.randomize();
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`checkd(rand_result, 0);
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obj = new();
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rand_result = obj.randomize();
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`checkd(rand_result, 1);
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`check_range(obj.value, 1, 199);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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