Suppress unsupported for unused constant sequences
This commit is contained in:
Wilson Snyder
parent
4dedfbfe08
commit
7957701db8
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@ -161,14 +161,15 @@ private:
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void visit(AstModportClockingRef* const nodep) override {
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// It has to be converted to a list of ModportClockingVarRefs,
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// because clocking blocks are removed in this pass
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for (AstClockingItem* itemp = nodep->clockingp()->itemsp(); itemp;
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itemp = VN_AS(itemp->nextp(), ClockingItem)) {
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AstVar* const varp = itemp->varp() ? itemp->varp() : VN_AS(itemp->user1p(), Var);
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if (varp) {
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AstModportVarRef* const modVarp
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= new AstModportVarRef{nodep->fileline(), varp->name(), itemp->direction()};
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modVarp->varp(varp);
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nodep->addNextHere(modVarp);
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for (AstNode* itemp = nodep->clockingp()->itemsp(); itemp; itemp = itemp->nextp()) {
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if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
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if (AstVar* const varp
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= citemp->varp() ? citemp->varp() : VN_AS(citemp->user1p(), Var)) {
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AstModportVarRef* const modVarp = new AstModportVarRef{
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nodep->fileline(), varp->name(), citemp->direction()};
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modVarp->varp(varp);
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nodep->addNextHere(modVarp);
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}
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}
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}
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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@ -765,15 +765,15 @@ class AstClocking final : public AstNode {
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// Parents: MODULE
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// Children: SENITEM, CLOCKING ITEMs, VARs
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// @astgen op1 := sensesp : AstSenItem
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// @astgen op2 := itemsp : List[AstClockingItem]
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// @astgen op2 := itemsp : List[AstNode]
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// @astgen op3 := eventp : Optional[AstVar]
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std::string m_name; // Clocking block name
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const bool m_isDefault; // True if default clocking
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const bool m_isGlobal; // True if global clocking
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public:
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AstClocking(FileLine* fl, const std::string& name, AstSenItem* sensesp,
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AstClockingItem* itemsp, bool isDefault, bool isGlobal)
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AstClocking(FileLine* fl, const std::string& name, AstSenItem* sensesp, AstNode* itemsp,
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bool isDefault, bool isGlobal)
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: ASTGEN_SUPER_Clocking(fl)
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, m_name{name}
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, m_isDefault{isDefault}
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@ -2347,6 +2347,22 @@ public:
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}
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string verilogKwd() const override { return "property"; }
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};
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class AstSequence final : public AstNodeFTask {
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// A sequence inside a module
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// TODO when supported might not want to be a NodeFTask
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bool m_referenced = false; // Ever referenced (for unsupported check)
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public:
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AstSequence(FileLine* fl, const string& name, AstNode* stmtp)
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: ASTGEN_SUPER_Sequence(fl, name, stmtp) {}
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ASTGEN_MEMBERS_AstSequence;
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bool hasDType() const override VL_MT_SAFE { return true; }
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AstNodeFTask* cloneType(const string& name) override {
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return new AstSequence{fileline(), name, nullptr};
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}
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string verilogKwd() const override { return "sequence"; }
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bool isReferenced() const { return m_referenced; }
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void isReferenced(bool flag) { m_referenced = flag; }
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};
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class AstTask final : public AstNodeFTask {
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// A task inside a module
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public:
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@ -931,28 +931,29 @@ class LinkParseVisitor final : public VNVisitor {
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VL_RESTORER(m_defaultInSkewp);
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VL_RESTORER(m_defaultOutSkewp);
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// Find default input and output skews
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AstClockingItem* nextItemp = nodep->itemsp();
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for (AstClockingItem* itemp = nextItemp; itemp; itemp = nextItemp) {
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nextItemp = VN_AS(itemp->nextp(), ClockingItem);
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if (itemp->exprp() || itemp->assignp()) continue;
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if (itemp->skewp()) {
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if (itemp->direction() == VDirection::INPUT) {
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// Disallow default redefinition; note some simulators allow this
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if (m_defaultInSkewp) {
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itemp->skewp()->v3error("Multiple default input skews not allowed");
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for (AstNode *nextp, *itemp = nodep->itemsp(); itemp; itemp = nextp) {
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nextp = itemp->nextp();
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if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
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if (citemp->exprp() || citemp->assignp()) continue;
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if (citemp->skewp()) {
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if (citemp->direction() == VDirection::INPUT) {
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// Disallow default redefinition; note some simulators allow this
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if (m_defaultInSkewp) {
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citemp->skewp()->v3error("Multiple default input skews not allowed");
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}
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m_defaultInSkewp = citemp->skewp();
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} else if (citemp->direction() == VDirection::OUTPUT) {
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// Disallow default redefinition; note some simulators allow this
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if (m_defaultOutSkewp) {
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citemp->skewp()->v3error("Multiple default output skews not allowed");
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}
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m_defaultOutSkewp = citemp->skewp();
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} else {
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citemp->v3fatalSrc("Incorrect direction");
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}
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m_defaultInSkewp = itemp->skewp();
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} else if (itemp->direction() == VDirection::OUTPUT) {
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// Disallow default redefinition; note some simulators allow this
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if (m_defaultOutSkewp) {
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itemp->skewp()->v3error("Multiple default output skews not allowed");
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}
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m_defaultOutSkewp = itemp->skewp();
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} else {
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itemp->v3fatalSrc("Incorrect direction");
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}
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VL_DO_DANGLING(pushDeletep(citemp->unlinkFrBack()), citemp);
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}
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VL_DO_DANGLING(pushDeletep(itemp->unlinkFrBack()), itemp);
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}
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iterateChildren(nodep);
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}
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@ -188,6 +188,10 @@ class LinkResolveVisitor final : public VNVisitor {
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}
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void visit(AstNodeFTaskRef* nodep) override {
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VL_RESTORER(m_currentRandomizeSelectp);
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if (nodep->taskp()) {
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if (AstSequence* const seqp = VN_CAST(nodep->taskp(), Sequence))
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seqp->isReferenced(true);
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}
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if (nodep->name() == "randomize") {
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if (const AstMethodCall* const methodcallp = VN_CAST(nodep, MethodCall)) {
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@ -3469,10 +3469,12 @@ class WidthVisitor final : public VNVisitor {
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AstVar* memberSelClocking(AstMemberSel* nodep, AstClocking* clockingp) {
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// Returns node if ok
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VSpellCheck speller;
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for (AstClockingItem* itemp = clockingp->itemsp(); itemp;
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itemp = VN_AS(itemp->nextp(), ClockingItem)) {
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if (itemp->varp()->name() == nodep->name()) return itemp->varp();
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speller.pushCandidate(itemp->varp()->prettyName());
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for (AstNode* itemp = clockingp->itemsp(); itemp; itemp = itemp->nextp()) {
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if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) {
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if (citemp->varp()->name() == nodep->name()) return citemp->varp();
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speller.pushCandidate(citemp->varp()->prettyName());
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}
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}
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const string suggest = speller.bestCandidateMsg(nodep->prettyName());
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nodep->v3error(
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@ -6462,6 +6464,15 @@ class WidthVisitor final : public VNVisitor {
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nodep->doingWidth(false);
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}
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void visit(AstReturn* nodep) override { nodep->v3fatalSrc("'return' missed in LinkJump"); }
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void visit(AstSequence* nodep) override {
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// UNSUPPORTED message is thrown only where the sequence is referenced
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// in order to enable some UVM tests.
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// When support more here will need finer-grained UNSUPPORTED if items
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// under the sequence are not supported
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if (nodep->isReferenced()) nodep->v3warn(E_UNSUPPORTED, "Unsupported: sequence");
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userIterateChildren(nodep, nullptr);
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if (!nodep->isReferenced()) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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}
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AstPackage* getItemPackage(AstNode* pkgItemp) {
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while (pkgItemp->backp() && pkgItemp->backp()->nextp() == pkgItemp) {
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@ -6127,17 +6127,17 @@ clocking_event<senItemp>: // IEEE: clocking_event
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| '@' '(' event_expression ')' { $$ = $3; }
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;
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clocking_itemListE<clockingItemp>:
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clocking_itemListE<nodep>:
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/* empty */ { $$ = nullptr; }
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| clocking_itemList { $$ = $1; }
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;
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clocking_itemList<clockingItemp>: // IEEE: [ clocking_item ]
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clocking_itemList<nodep>: // IEEE: [ clocking_item ]
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clocking_item { $$ = $1; }
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| clocking_itemList clocking_item { if ($1) $$ = addNextNull($1, $2); }
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;
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clocking_item<clockingItemp>: // IEEE: clocking_item
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clocking_item<nodep>: // IEEE: clocking_item
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yDEFAULT yINPUT clocking_skew ';' { $$ = new AstClockingItem{$<fl>1, VDirection::INPUT, $3, nullptr}; }
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| yDEFAULT yOUTPUT clocking_skew ';' { $$ = new AstClockingItem{$<fl>1, VDirection::OUTPUT, $3, nullptr}; }
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| yDEFAULT yINPUT clocking_skew yOUTPUT clocking_skew ';'
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@ -6154,8 +6154,16 @@ clocking_item<clockingItemp>: // IEEE: clocking_item
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{ $$ = GRAMMARP->makeClockingItemList($<fl>1, VDirection::INPUT, nullptr, $2->cloneTree(true));
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$$->addNext(GRAMMARP->makeClockingItemList($<fl>1, VDirection::OUTPUT, nullptr, $2)); }
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| assertion_item_declaration
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{ $$ = nullptr;
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BBUNSUP($1, "Unsupported: assertion items in clocking blocks"); DEL($1); }
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{ $$ = $1;
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for (AstNode* nodep = $1; nodep; nodep = nodep->nextp()) {
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if (!VN_IS(nodep, Sequence)) {
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$$ = nullptr;
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BBUNSUP(nodep, "Unsupported: assertion items in clocking blocks");
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DEL($1);
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break;
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}
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}
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}
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;
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list_of_clocking_decl_assign<nodep>: // IEEE: list_of_clocking_decl_assign
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@ -6395,13 +6403,16 @@ sequence_declaration<nodeFTaskp>: // ==IEEE: sequence_declaration
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{ $$ = $1;
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$$->addStmtsp($2);
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$$->addStmtsp($4);
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GRAMMARP->endLabel($<fl>6, $$, $6); }
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GRAMMARP->endLabel($<fl>6, $$, $6);
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// No error on UVM special case with no reference; see t_sequence_unused.v
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if (! (!$$->stmtsp() || (VN_IS($$->stmtsp(), Const) && !$$->stmtsp()->nextp())))
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$$->v3warn(E_UNSUPPORTED, "Unsupported: sequence");
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}
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;
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sequence_declarationFront<nodeFTaskp>: // IEEE: part of sequence_declaration
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ySEQUENCE idAny/*new_sequence*/
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{ BBUNSUP($1, "Unsupported: sequence");
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$$ = new AstProperty{$<fl>2, *$2, nullptr}; }
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{ $$ = new AstSequence{$<fl>2, *$2, nullptr}; }
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;
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sequence_port_listE<nodep>: // IEEE: [ ( [ sequence_port_list ] ) ]
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@ -0,0 +1,6 @@
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%Error-UNSUPPORTED: t/t_sequence_ref_unsup.v:9:12: Unsupported: sequence
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: ... note: In instance 't'
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9 | sequence s_one;
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| ^~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(expect_filename=test.golden_filename, verilator_flags2=['--timing'], fails=True)
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test.passes()
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@ -0,0 +1,19 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sequence s_one;
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1;
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endsequence
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initial begin
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@s_one;
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$display("got sequence");
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$finish;
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end
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endmodule
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@ -1,175 +1,175 @@
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:4: Unsupported: sequence
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:13: Unsupported: sequence
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27 | sequence s_a;
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| ^~~~~~~~
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| ^~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:4: Unsupported: sequence
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:13: Unsupported: sequence
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30 | sequence s_var;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:4: Unsupported: sequence
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35 | sequence s_within;
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| ^~~~~~~~
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| ^~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:36:9: Unsupported: within (in sequence expression)
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36 | a within(b);
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:4: Unsupported: sequence
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39 | sequence s_and;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:13: Unsupported: sequence
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35 | sequence s_within;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:40:9: Unsupported: and (in sequence expression)
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40 | a and b;
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| ^~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:4: Unsupported: sequence
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43 | sequence s_or;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:13: Unsupported: sequence
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39 | sequence s_and;
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| ^~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:44:9: Unsupported: or (in sequence expression)
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44 | a or b;
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| ^~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:4: Unsupported: sequence
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47 | sequence s_throughout;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:13: Unsupported: sequence
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43 | sequence s_or;
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| ^~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:48:9: Unsupported: throughout (in sequence expression)
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48 | a throughout b;
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| ^~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:4: Unsupported: sequence
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51 | sequence s_intersect;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:13: Unsupported: sequence
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47 | sequence s_throughout;
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| ^~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:52:9: Unsupported: intersect (in sequence expression)
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52 | a intersect b;
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| ^~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:4: Unsupported: sequence
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:13: Unsupported: sequence
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51 | sequence s_intersect;
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| ^~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:13: Unsupported: sequence
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55 | sequence s_uni_cycdelay_id;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:4: Unsupported: sequence
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| ^~~~~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:13: Unsupported: sequence
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58 | sequence s_uni_cycdelay_pid;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:4: Unsupported: sequence
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61 | sequence s_uni_cycdelay_range;
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| ^~~~~~~~
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| ^~~~~~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:7: Unsupported: ## range cycle delay range expression
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62 | ## [1:2] b;
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| ^~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:4: Unsupported: sequence
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64 | sequence s_uni_cycdelay_star;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:13: Unsupported: sequence
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61 | sequence s_uni_cycdelay_range;
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| ^~~~~~~~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:65:7: Unsupported: ## [*] cycle delay range expression
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65 | ## [*] b;
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| ^~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:4: Unsupported: sequence
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67 | sequence s_uni_cycdelay_plus;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:13: Unsupported: sequence
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64 | sequence s_uni_cycdelay_star;
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| ^~~~~~~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:68:7: Unsupported: ## [+] cycle delay range expression
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68 | ## [+] b;
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| ^~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:4: Unsupported: sequence
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:13: Unsupported: sequence
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67 | sequence s_uni_cycdelay_plus;
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| ^~~~~~~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:13: Unsupported: sequence
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71 | sequence s_cycdelay_id;
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| ^~~~~~~~
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:4: Unsupported: sequence
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| ^~~~~~~~~~~~~
|
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%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:13: Unsupported: sequence
|
||||
74 | sequence s_cycdelay_pid;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:4: Unsupported: sequence
|
||||
77 | sequence s_cycdelay_range;
|
||||
| ^~~~~~~~
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:9: Unsupported: ## range cycle delay range expression
|
||||
78 | a ## [1:2] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:4: Unsupported: sequence
|
||||
80 | sequence s_cycdelay_star;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:13: Unsupported: sequence
|
||||
77 | sequence s_cycdelay_range;
|
||||
| ^~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:9: Unsupported: ## [*] cycle delay range expression
|
||||
81 | a ## [*] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:4: Unsupported: sequence
|
||||
83 | sequence s_cycdelay_plus;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:13: Unsupported: sequence
|
||||
80 | sequence s_cycdelay_star;
|
||||
| ^~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:84:9: Unsupported: ## [+] cycle delay range expression
|
||||
84 | a ## [+] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:4: Unsupported: sequence
|
||||
87 | sequence s_booleanabbrev_brastar_int;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:13: Unsupported: sequence
|
||||
83 | sequence s_cycdelay_plus;
|
||||
| ^~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:9: Unsupported: [*] boolean abbrev expression
|
||||
88 | a [* 1 ];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:12: Unsupported: boolean abbrev (in sequence expression)
|
||||
88 | a [* 1 ];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:4: Unsupported: sequence
|
||||
90 | sequence s_booleanabbrev_brastar;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:13: Unsupported: sequence
|
||||
87 | sequence s_booleanabbrev_brastar_int;
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: [*] boolean abbrev expression
|
||||
91 | a [*];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: boolean abbrev (in sequence expression)
|
||||
91 | a [*];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:4: Unsupported: sequence
|
||||
93 | sequence s_booleanabbrev_plus;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:13: Unsupported: sequence
|
||||
90 | sequence s_booleanabbrev_brastar;
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: [+] boolean abbrev expression
|
||||
94 | a [+];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: boolean abbrev (in sequence expression)
|
||||
94 | a [+];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:4: Unsupported: sequence
|
||||
96 | sequence s_booleanabbrev_eq;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:13: Unsupported: sequence
|
||||
93 | sequence s_booleanabbrev_plus;
|
||||
| ^~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: [= boolean abbrev expression
|
||||
97 | a [= 1];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:12: Unsupported: boolean abbrev (in sequence expression)
|
||||
97 | a [= 1];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:4: Unsupported: sequence
|
||||
99 | sequence s_booleanabbrev_eq_range;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:13: Unsupported: sequence
|
||||
96 | sequence s_booleanabbrev_eq;
|
||||
| ^~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [= boolean abbrev expression
|
||||
100 | a [= 1:2];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: boolean abbrev (in sequence expression)
|
||||
100 | a [= 1:2];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:4: Unsupported: sequence
|
||||
102 | sequence s_booleanabbrev_minusgt;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:13: Unsupported: sequence
|
||||
99 | sequence s_booleanabbrev_eq_range;
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [-> boolean abbrev expression
|
||||
103 | a [-> 1];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:13: Unsupported: boolean abbrev (in sequence expression)
|
||||
103 | a [-> 1];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:4: Unsupported: sequence
|
||||
105 | sequence s_booleanabbrev_minusgt_range;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:13: Unsupported: sequence
|
||||
102 | sequence s_booleanabbrev_minusgt;
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:9: Unsupported: [-> boolean abbrev expression
|
||||
106 | a [-> 1:2];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:13: Unsupported: boolean abbrev (in sequence expression)
|
||||
106 | a [-> 1:2];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:4: Unsupported: sequence
|
||||
109 | sequence p_arg_seqence(sequence inseq);
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:13: Unsupported: sequence
|
||||
105 | sequence s_booleanabbrev_minusgt_range;
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:27: Unsupported: sequence argument data type
|
||||
109 | sequence p_arg_seqence(sequence inseq);
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:113:4: Unsupported: sequence
|
||||
113 | sequence s_firstmatch_a;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:13: Unsupported: sequence
|
||||
109 | sequence p_arg_seqence(sequence inseq);
|
||||
| ^~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:7: Unsupported: first_match (in sequence expression)
|
||||
114 | first_match (a);
|
||||
| ^~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:4: Unsupported: sequence
|
||||
116 | sequence s_firstmatch_ab;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:113:13: Unsupported: sequence
|
||||
113 | sequence s_firstmatch_a;
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:117:7: Unsupported: first_match (in sequence expression)
|
||||
117 | first_match (a, res0 = 1);
|
||||
| ^~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:4: Unsupported: sequence
|
||||
119 | sequence s_firstmatch_abc;
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:13: Unsupported: sequence
|
||||
116 | sequence s_firstmatch_ab;
|
||||
| ^~~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:120:7: Unsupported: first_match (in sequence expression)
|
||||
120 | first_match (a, res0 = 1, res1 = 2);
|
||||
| ^~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:13: Unsupported: sequence
|
||||
119 | sequence s_firstmatch_abc;
|
||||
| ^~~~~~~~~~~~~~~~
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:10: Ignoring unsupported: cover sequence
|
||||
123 | cover sequence (s_a) $display("");
|
||||
| ^~~~~~~~
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface apb_if (
|
||||
input bit clk
|
||||
);
|
||||
wire [31:0] paddr;
|
||||
wire [31:0] prdata;
|
||||
|
||||
clocking mck @(posedge clk);
|
||||
output paddr;
|
||||
input prdata;
|
||||
|
||||
// Some UVM tests declare this sequence but never use it
|
||||
// so we defer UNSUPPORTED until usage point
|
||||
sequence at_posedge;
|
||||
1;
|
||||
endsequence : at_posedge
|
||||
endclocking
|
||||
|
||||
endinterface
|
||||
|
||||
module t (
|
||||
input clk
|
||||
);
|
||||
|
||||
apb_if ifc(clk);
|
||||
|
||||
initial $finish;
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue