Fix Dfg reusing volatile variables

Forceable/externally written variables cannot be used as the canonical
result variable for a Dfg value as the variables value can be
inconsistent with its Dfg drivers (e.g. when forced).
This commit is contained in:
Geza Lore 2025-12-05 12:25:55 +00:00
parent cfada791e6
commit df7726c40d
4 changed files with 90 additions and 7 deletions

View File

@ -552,6 +552,10 @@ DfgVertexVar* DfgVertex::getResultVar() {
this->foreachSink([&resp](DfgVertex& sink) {
DfgVertexVar* const varp = sink.cast<DfgVertexVar>();
if (!varp) return false;
// Do not use it if value might differ from its drivers
if (varp->isVolatile()) return false;
// First variable found
if (!resp) {
resp = varp;
@ -559,12 +563,8 @@ DfgVertexVar* DfgVertex::getResultVar() {
}
// Prefer those variables that must be kept anyway
if (resp->hasExtRefs() != varp->hasExtRefs()) {
if (!resp->hasExtRefs()) resp = varp;
return false;
}
if (resp->hasModWrRefs() != varp->hasModWrRefs()) {
if (!resp->hasModWrRefs()) resp = varp;
if (resp->hasExtRdRefs() != varp->hasExtRdRefs()) {
if (!resp->hasExtRdRefs()) resp = varp;
return false;
}
if (resp->hasDfgRefs() != varp->hasDfgRefs()) {

View File

@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

View File

@ -0,0 +1,65 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
module top;
logic clk = 0;
always #5 clk = ~clk;
int cnt = 0;
always @(posedge clk) cnt <= cnt + 1;
wire forcedVar = &cnt[2:1];
wire sharedTerm = &cnt[2:1];
wire otherVar = ~sharedTerm;
initial begin
repeat (50) begin
@(posedge clk);
`check(otherVar == ~forcedVar, 1);
end
force forcedVar = 1'b1;
repeat (50) begin
@(posedge clk);
`check(otherVar == ~forcedVar, cnt[2] & cnt[1]);
end
release forcedVar;
repeat (50) begin
@(posedge clk);
`check(otherVar == ~forcedVar, 1);
end
force forcedVar = 1'b0;
repeat (50) begin
@(posedge clk);
`check(otherVar == ~forcedVar, ~cnt[2] | ~cnt[1]);
end
release forcedVar;
repeat (50) begin
@(posedge clk);
`check(otherVar == ~forcedVar, 1);
end
$write("*-* All Finished *-*\n");
$finish;
end
always @(sharedTerm or otherVar) begin
`check(otherVar, ~sharedTerm);
end
endmodule

View File

@ -42,7 +42,7 @@ if test.vlt_all:
# We expect to combine sequent functions across multiple instances of
# l2, l3, l4, l5. If this number drops, please confirm this has not broken.
test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)',
(99 if test.vltmt else 82))
(85 if test.vltmt else 67))
# Everything should use relative references
check_relative_refs("t", True)