Fix Dfg reusing volatile variables
Forceable/externally written variables cannot be used as the canonical result variable for a Dfg value as the variables value can be inconsistent with its Dfg drivers (e.g. when forced).
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@ -552,6 +552,10 @@ DfgVertexVar* DfgVertex::getResultVar() {
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this->foreachSink([&resp](DfgVertex& sink) {
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DfgVertexVar* const varp = sink.cast<DfgVertexVar>();
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if (!varp) return false;
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// Do not use it if value might differ from its drivers
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if (varp->isVolatile()) return false;
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// First variable found
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if (!resp) {
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resp = varp;
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@ -559,12 +563,8 @@ DfgVertexVar* DfgVertex::getResultVar() {
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}
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// Prefer those variables that must be kept anyway
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if (resp->hasExtRefs() != varp->hasExtRefs()) {
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if (!resp->hasExtRefs()) resp = varp;
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return false;
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}
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if (resp->hasModWrRefs() != varp->hasModWrRefs()) {
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if (!resp->hasModWrRefs()) resp = varp;
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if (resp->hasExtRdRefs() != varp->hasExtRdRefs()) {
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if (!resp->hasExtRdRefs()) resp = varp;
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return false;
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}
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if (resp->hasDfgRefs() != varp->hasDfgRefs()) {
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,65 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
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module top;
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logic clk = 0;
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always #5 clk = ~clk;
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int cnt = 0;
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always @(posedge clk) cnt <= cnt + 1;
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wire forcedVar = &cnt[2:1];
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wire sharedTerm = &cnt[2:1];
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wire otherVar = ~sharedTerm;
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initial begin
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repeat (50) begin
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@(posedge clk);
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`check(otherVar == ~forcedVar, 1);
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end
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force forcedVar = 1'b1;
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repeat (50) begin
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@(posedge clk);
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`check(otherVar == ~forcedVar, cnt[2] & cnt[1]);
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end
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release forcedVar;
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repeat (50) begin
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@(posedge clk);
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`check(otherVar == ~forcedVar, 1);
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end
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force forcedVar = 1'b0;
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repeat (50) begin
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@(posedge clk);
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`check(otherVar == ~forcedVar, ~cnt[2] | ~cnt[1]);
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end
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release forcedVar;
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repeat (50) begin
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@(posedge clk);
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`check(otherVar == ~forcedVar, 1);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(sharedTerm or otherVar) begin
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`check(otherVar, ~sharedTerm);
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end
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endmodule
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@ -42,7 +42,7 @@ if test.vlt_all:
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# We expect to combine sequent functions across multiple instances of
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# l2, l3, l4, l5. If this number drops, please confirm this has not broken.
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test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)',
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(99 if test.vltmt else 82))
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(85 if test.vltmt else 67))
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# Everything should use relative references
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check_relative_refs("t", True)
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