Verilog format

test_regress/t/t_concat_init_array_functions.v

@@ -19,12 +19,12 @@ class B;
 endclass
 
 function int func_1_concat(int r[4]);
-// verilator no_inline_task
+  // verilator no_inline_task
   return r[0] + r[1] + r[2] + r[3];
 endfunction
 
 function int func_2_concat(int r[3], int p[4]);
-// verilator no_inline_task
+  // verilator no_inline_task
   return r[0] + r[1] + r[2] + p[0] + p[1] + p[2] + p[3];
 endfunction
 
@@ -33,7 +33,7 @@ module t;
   A a = new;
   B b = new;
   initial begin
-    a.r1 = {1,2};
+    a.r1 = {1, 2};
     a.r2 = 5;
     s = func_1_concat({a.r1, a.r1});
     if (s != 6) $stop;

test_regress/t/t_constraint_unsup_unq_arr.v

@@ -23,7 +23,7 @@ class UniqueMultipleArray;
     unique {uniq_val_hash};  // Ensure unique values in the array
     unique {uniq_val_queue};  // Ensure unique values in the array
     unique {uniq_val_arr_mda};  // Ensure unique values in the array
-    unique { array[0], array[1] };
+    unique {array[0], array[1]};
   }
   // --------------------------------------------------
   // Explicit uniqueness checker (post-solve validation)
@@ -32,7 +32,8 @@ class UniqueMultipleArray;
     for (int i = 0; i < $size(uniq_val_arr); i++) begin
       for (int j = i + 1; j < $size(uniq_val_arr); j++) begin
         if (uniq_val_arr[i] == uniq_val_arr[j]) begin
-          $error("UNIQUENESS VIOLATION: uniq_val_arr[%0d] == uniq_val_arr[%0d] == 0x%h", i, j, uniq_val_arr[i]);
+          $error("UNIQUENESS VIOLATION: uniq_val_arr[%0d] == uniq_val_arr[%0d] == 0x%h", i, j,
+                 uniq_val_arr[i]);
           return 0;
         end
       end

test_regress/t/t_pattern_unsup_xor.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:13:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR
+%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:11:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR
                                                  : ... note: In instance 't'
-   13 |   status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
+   11 |   status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
       |                         ^~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_pattern_unsup_xor.v

@@ -6,9 +6,7 @@
 
 // Test for issue where assignment pattern with XOR caused segfault
 module t;
-  typedef struct {
-    logic bit_field;
-  } status_t;
+  typedef struct {logic bit_field;} status_t;
 
   status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
 endmodule

test_regress/t/t_scheduling_7.v

@@ -19,7 +19,7 @@ endtask
 
 class Foo;
   task run_phases();
-    repeat(2) begin
+    repeat (2) begin
       fork
         if ($c(1)) wait_for_nba_region();
       join_none