Fix firing array selects of events (#6829).
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@ -110,6 +110,7 @@ Verilator 5.043 devel
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* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
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* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
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* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
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* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
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Verilator 5.042 2025-11-02
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@ -741,6 +741,10 @@ class WidthVisitor final : public VNVisitor {
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if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBackWithNext());
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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}
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void visit(AstFireEvent* nodep) override {
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assertAtStatement(nodep);
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iterateCheckSelf(nodep, "LHS", nodep->operandp(), SELF, BOTH);
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}
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void visit(AstFork* nodep) override {
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if (!m_underFork && VN_IS(m_ftaskp, Func) && !nodep->joinType().joinNone()) {
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nodep->v3error("Only fork .. join_none is legal in functions. "
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,65 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
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// verilog_format: on
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module t;
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event e_all_xfers_monitored_tx[4];
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event e_all_xfers_monitored_rx[4];
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event e_all_xfers_completed[4];
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task automatic debug(string s);
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$display("%s", s);
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endtask
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task run_traffic_per_port(int port_id);
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fork
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automatic int id = port_id;
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begin
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fork
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begin
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@(e_all_xfers_monitored_tx[id]);
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debug($sformatf("[%0t] [Port %0d] TX done", $time, id));
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end
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begin
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@(e_all_xfers_monitored_rx[id]);
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debug($sformatf("[%0t] [Port %0d] RX done", $time, id));
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end
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join
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->e_all_xfers_completed[id];
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$display("[%0t] [Port %0d] ALL done", $time, id);
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end
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join_none
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endtask
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initial begin
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int i;
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for (i = 0; i < 2; i++) begin
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run_traffic_per_port(i);
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end
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#10->e_all_xfers_monitored_tx[0];
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#10->e_all_xfers_monitored_rx[0];
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#10->e_all_xfers_monitored_tx[1];
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#10->e_all_xfers_monitored_rx[1];
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@(e_all_xfers_completed[0]);
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@(e_all_xfers_completed[1]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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