Fix firing array selects of events (#6829).

This commit is contained in:
Wilson Snyder 2025-12-18 20:45:22 -05:00
parent 24e43f4ddd
commit c2c00888d6
4 changed files with 88 additions and 0 deletions

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@ -110,6 +110,7 @@ Verilator 5.043 devel
* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
Verilator 5.042 2025-11-02

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@ -741,6 +741,10 @@ class WidthVisitor final : public VNVisitor {
if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBackWithNext());
VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
}
void visit(AstFireEvent* nodep) override {
assertAtStatement(nodep);
iterateCheckSelf(nodep, "LHS", nodep->operandp(), SELF, BOTH);
}
void visit(AstFork* nodep) override {
if (!m_underFork && VN_IS(m_ftaskp, Func) && !nodep->joinType().joinNone()) {
nodep->v3error("Only fork .. join_none is legal in functions. "

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--binary'])
test.execute()
test.passes()

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@ -0,0 +1,65 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t;
event e_all_xfers_monitored_tx[4];
event e_all_xfers_monitored_rx[4];
event e_all_xfers_completed[4];
task automatic debug(string s);
$display("%s", s);
endtask
task run_traffic_per_port(int port_id);
fork
automatic int id = port_id;
begin
fork
begin
@(e_all_xfers_monitored_tx[id]);
debug($sformatf("[%0t] [Port %0d] TX done", $time, id));
end
begin
@(e_all_xfers_monitored_rx[id]);
debug($sformatf("[%0t] [Port %0d] RX done", $time, id));
end
join
->e_all_xfers_completed[id];
$display("[%0t] [Port %0d] ALL done", $time, id);
end
join_none
endtask
initial begin
int i;
for (i = 0; i < 2; i++) begin
run_traffic_per_port(i);
end
#10->e_all_xfers_monitored_tx[0];
#10->e_all_xfers_monitored_rx[0];
#10->e_all_xfers_monitored_tx[1];
#10->e_all_xfers_monitored_rx[1];
@(e_all_xfers_completed[0]);
@(e_all_xfers_completed[1]);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule