Commentary: Changes update
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Changes
9
Changes
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@ -65,7 +65,9 @@ Verilator 5.047 devel
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* Optimize DFG peephole until a fixed point (#7309). [Geza Lore, Testorrent USA, Inc.]
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* Optimize comparisons with identical operands and $countones in DFG. [Geza Lore, Testorrent USA, Inc.]
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* Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.]
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* Optimize read references in DFG (#7354). [Geza Lore, Testorrent USA, Inc.]
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* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
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* Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
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* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
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* Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
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* Fix null assignment to virtual interfaces (#5974) (#5990). [Maxim Fonarev]
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@ -85,9 +87,11 @@ Verilator 5.047 devel
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* Fix wide conditional short circuiting (#7155).
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* Fix eliminating assignments to DPI-read variables (#7158). [Geza Lore, Testorrent USA, Inc.]
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* Fix std::randomize() in static function with static class members (#7167) (#7169). [Yilou Wang]
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* Fix resolving default/non-default type parameters (#7171) (#7346). [em2machine]
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* Fix recursive constant function in $unit scope (#7173) (#7174).
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* Fix class extend references between queues (#7195).
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* Fix library/hier_block tracing when top name is empty (#7200). [Geza Lore, Testorrent USA, Inc.]
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* Fix virtual interface select from sub-interface instance (#7203) (#7370) (#7203). [Yilou Wang]
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* Fix VPI force of bit-selected signals (#7211) (#7301). [Christian Hecken]
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* Fix wrong $bits() for parameterized interface struct typedefs (#7218) (#7219). [em2machine]
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* Fix `dist` operator inside constraint if blocks (#7221) (#7224). [Rahul Behl, Testorrent USA, Inc.]
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@ -96,6 +100,7 @@ Verilator 5.047 devel
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* Fix internal error when derived class calls this.randomize() with inherited rand members (#7229) (#7234). [Yilou Wang]
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* Fix enum range constraints missing for rand variables in sub-objects (#7230) (#7235). [Yilou Wang]
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* Fix vpi_put_value release on non-continuous signal (#7231) (#7241). [Christian Hecken]
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* Fix functions in generate block resulting in 'Broken link in node' (#7236) (#7367). [em2machine]
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* Fix tracing of typedefed 1D packed arrays with --trace-structs (#7237). [Geza Lore, Testorrent USA, Inc.]
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* Fix rand variable used as array index in constraint evaluated as constant (#7238) (#7247). [Yilou Wang]
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* Fix --hierarchical dropping arguments in -f/-F files (#7240). [Clara Sparks]
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@ -113,6 +118,10 @@ Verilator 5.047 devel
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* Fix lost `$stop` on implied assertion `$error` failures.
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* Fix wait() hang when interface uses process calls and VIF function (#7342). [Yilou Wang]
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* Fix error on illegal nand/nor binary operators (#7353).
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* Fix simple array assignment unrolling in slice optimization (#7359). [Geza Lore, Testorrent USA, Inc.]
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* Fix missing temporary for DfgSplicePacked (#7361). [Geza Lore, Testorrent USA, Inc.]
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* Fix virtual interface function calls binding to wrong instance (#7363). [Yilou Wang]
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* Fix false ASSIGNIN on interface input port connections (#7365). [Yilou Wang]
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Verilator 5.046 2026-02-28
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@ -8,16 +8,20 @@
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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package p;
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class W #(type T = int);
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class W #(
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type T = int
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);
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T v;
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endclass
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class Holder #(type U = W#());
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class Holder #(
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type U = W#()
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);
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U u;
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endclass
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typedef Holder#() H_imp_t; // implicit default
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typedef Holder#(W#(int)) H_exp_t; // explicit equivalent default
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typedef Holder#() H_imp_t; // implicit default
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typedef Holder#(W#(int)) H_exp_t; // explicit equivalent default
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endpackage
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module t;
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@ -29,8 +33,8 @@ module t;
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// verilator lint_off CASTCONST
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// verilator lint_off WIDTHTRUNC
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if (!$cast(exp, imp)) begin
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// verilator lint_on WIDTHTRUNC
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// verilator lint_on CASTCONST
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// verilator lint_on WIDTHTRUNC
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// verilator lint_on CASTCONST
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$display("WRONG_TYPE");
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$fatal;
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end
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@ -11,13 +11,14 @@
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t(/*AUTOARG*/);
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module t ( /*AUTOARG*/);
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generate
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if (1) begin : defs
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function automatic logic foo;
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foo = 1'b1;
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endfunction
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end else begin : defs
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end
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else begin : defs
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function automatic logic foo;
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foo = 1'b0;
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endfunction
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@ -6,7 +6,7 @@
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interface my_if;
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logic clk = 0;
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bit clk_active = 0;
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bit clk_active = 0;
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initial begin
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wait (clk_active);
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@ -27,8 +27,8 @@ class Driver;
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endclass
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module t;
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my_if intf();
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my_if intf_unused(); // Second instance triggered the bug
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my_if intf ();
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my_if intf_unused (); // Second instance triggered the bug
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initial begin
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automatic Driver d = new;
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@ -9,7 +9,7 @@ interface str_if;
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endinterface
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module t;
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str_if sif();
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str_if sif ();
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virtual str_if vif = sif;
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initial begin
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