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@ -2368,9 +2368,8 @@ class ConstraintExprVisitor final : public VNVisitor {
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const std::string smtArrayName = arrVarp->name();
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AstNodeDType* elemDtp = arrVarp->dtypep()->skipRefp()->subDTypep();
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const int elemWidth = elemDtp->width();
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AstNodeModule* const classModulep = m_classp
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? static_cast<AstNodeModule*>(m_classp)
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: VN_AS(m_genp->user2p(), NodeModule);
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AstNodeModule* const arrModulep = VN_AS(arrVarp->user2p(), NodeModule);
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AstNodeModule* const genModulep = VN_AS(m_genp->user2p(), NodeModule);
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arrVarp->user3(true);
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// Create variable name using AstSFormatF
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@ -2379,7 +2378,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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// Create array element reference: array.atWrite(index)
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AstCMethodHard* const atWritep = new AstCMethodHard{
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fl, new AstVarRef{fl, classModulep, arrVarp, VAccess::READWRITE},
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fl, new AstVarRef{fl, arrModulep, arrVarp, VAccess::READWRITE},
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VCMethod::ARRAY_AT_WRITE, new AstVarRef{fl, loopVarp, VAccess::READ}};
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atWritep->dtypeFrom(elemDtp);
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@ -2392,7 +2391,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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// Create write_var method call: gen.write_var(arrElement, width, name, 0)
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AstCMethodHard* const writeVarp = new AstCMethodHard{
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fl, new AstVarRef{fl, classModulep, m_genp, VAccess::READWRITE},
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fl, new AstVarRef{fl, genModulep, m_genp, VAccess::READWRITE},
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VCMethod::RANDOMIZER_WRITE_VAR, atWritep};
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writeVarp->addPinsp(new AstConst{fl, AstConst::WidthedValue{}, 64,
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static_cast<uint32_t>(elemWidth)});
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,75 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test array reduction methods in constraints with class inheritance (issue #7226)
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// The bug was that .sum() in a constraint crashed with "Can't locate varref scope"
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// when the class extends another class.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Base;
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rand int base_val;
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constraint c_base {base_val inside {[1:100]};}
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endclass
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// Derived class with dynamic array and .sum() constraint -- the crash scenario
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class Derived extends Base;
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rand int arr[];
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constraint c_size {arr.size() == 4;}
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constraint c_sum {arr.sum() == 200;}
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function new();
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arr = new[4];
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endfunction
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endclass
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// Multi-level inheritance: ensure deeper hierarchies also work
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class GrandChild extends Derived;
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rand bit [7:0] extra[3];
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constraint c_extra_or {extra.or() != 0;}
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endclass
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module t;
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initial begin
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static Derived d = new();
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static GrandChild g = new();
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int sum_check;
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// Test single-level inheritance with .sum()
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repeat (5) begin
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`checkd(d.randomize(), 1)
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`checkd(d.arr.size(), 4)
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sum_check = 0;
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foreach (d.arr[i]) sum_check += d.arr[i];
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`checkd(sum_check, 200)
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`checkd(d.base_val inside {[1:100]}, 1)
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end
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// Test multi-level inheritance with reduction on fixed array
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repeat (5) begin
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bit [7:0] or_check;
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`checkd(g.randomize(), 1)
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`checkd(g.arr.size(), 4)
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sum_check = 0;
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foreach (g.arr[i]) sum_check += g.arr[i];
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`checkd(sum_check, 200)
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or_check = 0;
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foreach (g.extra[i]) or_check |= g.extra[i];
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if (or_check == 0) begin
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$write("%%Error: %s:%0d: extra.or() should be nonzero\n", `__FILE__, `__LINE__);
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`stop;
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end
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`checkd(g.base_val inside {[1:100]}, 1)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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