Commentary: Changes update

Changes

@@ -43,8 +43,9 @@ Verilator 5.047 devel
 * Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
 * Support property-local variables and sequence match items (#7286). [Yilou Wang]
 * Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
+* Support consecutive repetition `[\*N]` in SVA properties (#7311). [Yilou Wang]
 * Support `##[M:N]` range cycle delay in SVA sequences (#7312). [Yilou Wang]
-* Support array map() method (#7307) (#7316). [Wei-Lun Chiu]
+* Support array map() method (#7307) (#7316) (#7344). [Wei-Lun Chiu]
 * Add VPI callback support to --main (#7145).
 * Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
 * Add --func-recursion-depth CLI option (#7175) (#7179).
@@ -106,8 +107,10 @@ Verilator 5.047 devel
 * Fix modport selection of virtual interface handle (#7321). [Yilou Wang]
 * Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
 * Fix static initialization order for packages with class hierarchies (#7324). [Yilou Wang]
+* Fix sensitivity of signals to unrelated interface members (#7336). [Artur Bieniek, Antmicro Ltd.]
 * Fix `disable iff` imply-delay statement linking (#7337). [Nick Brereton]
 * Fix lost `$stop` on implied assertion `$error` failures.
+* Fix wait() hang when interface uses process calls and VIF function (#7342). [Yilou Wang]
 
 
 Verilator 5.046 2026-02-28

test_regress/t/t_assert_prop_consec_rep.v

@@ -30,29 +30,28 @@ module t (
   int count_fail5 = 0;
 
   // Test 1: a[*3] |-> b (3 consecutive, overlapping implication)
-  assert property (@(posedge clk) a[*3] |-> b)
-    else count_fail1 <= count_fail1 + 1;
+  assert property (@(posedge clk) a [* 3] |-> b)
+  else count_fail1 <= count_fail1 + 1;
 
   // Test 2: a[*1] |-> c (trivial [*1], overlapping)
-  assert property (@(posedge clk) a[*1] |-> c)
-    else count_fail2 <= count_fail2 + 1;
+  assert property (@(posedge clk) a [* 1] |-> c)
+  else count_fail2 <= count_fail2 + 1;
 
   // Test 3: a[*2] |=> d (2 consecutive, non-overlapping implication)
-  assert property (@(posedge clk) a[*2] |=> d)
-    else count_fail3 <= count_fail3 + 1;
+  assert property (@(posedge clk) a [* 2] |=> d)
+  else count_fail3 <= count_fail3 + 1;
 
   // Test 4: standalone consecutive rep (no implication)
-  assert property (@(posedge clk) b[*2])
-    else count_fail4 <= count_fail4 + 1;
+  assert property (@(posedge clk) b [* 2])
+  else count_fail4 <= count_fail4 + 1;
 
   // Test 5: [*10000] large count -- verifies counter-based lowering compiles
-  assert property (@(posedge clk) a[*10000] |-> b)
-    else count_fail5 <= count_fail5 + 1;
+  assert property (@(posedge clk) a [* 10000] |-> b)
+  else count_fail5 <= count_fail5 + 1;
 
   always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
-           $time, cyc, crc, a, b, c, d);
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};

test_regress/t/t_assert_prop_consec_rep_bad.out

@@ -1,15 +1,15 @@
-%Error: t/t_assert_prop_consec_rep_bad.v:12:39: Expecting expression to be constant, but variable isn't const: 'n'
+%Error: t/t_assert_prop_consec_rep_bad.v:14:40: Expecting expression to be constant, but variable isn't const: 'n'
                                               : ... note: In instance 't'
-   12 |   assert property (@(posedge clk) a [*n] |-> 1);
-      |                                       ^
+   14 |   assert property (@(posedge clk) a [* n] |-> 1);
+      |                                        ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_assert_prop_consec_rep_bad.v:12:37: Consecutive repetition count must be constant expression (IEEE 1800-2023 16.9.2)
+%Error: t/t_assert_prop_consec_rep_bad.v:14:37: Consecutive repetition count must be constant expression (IEEE 1800-2023 16.9.2)
                                               : ... note: In instance 't'
-   12 |   assert property (@(posedge clk) a [*n] |-> 1);
+   14 |   assert property (@(posedge clk) a [* n] |-> 1);
       |                                     ^~
-%Error-UNSUPPORTED: t/t_assert_prop_consec_rep_bad.v:15:37: Unsupported: [*0] consecutive repetition
+%Error-UNSUPPORTED: t/t_assert_prop_consec_rep_bad.v:17:37: Unsupported: [*0] consecutive repetition
                                                           : ... note: In instance 't'
-   15 |   assert property (@(posedge clk) a [*0] |-> 1);
+   17 |   assert property (@(posedge clk) a [* 0] |-> 1);
       |                                     ^~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_assert_prop_consec_rep_bad.v

@@ -4,14 +4,16 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 
-module t (input clk);
+module t (
+    input clk
+);
   logic a;
   int n;
 
   // Bad: non-constant repetition count
-  assert property (@(posedge clk) a [*n] |-> 1);
+  assert property (@(posedge clk) a [* n] |-> 1);
 
   // Bad: [*0] consecutive repetition unsupported
-  assert property (@(posedge clk) a [*0] |-> 1);
+  assert property (@(posedge clk) a [* 0] |-> 1);
 
 endmodule

test_regress/t/t_virtual_interface_unused_task_trigger.v

@@ -4,43 +4,43 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-module leaf(
+module leaf (
     input sel,
     output logic ready
 );
-    always @(sel)
-        if ((sel == 1))
-            ready = 1;
+  always @(sel) if ((sel == 1)) ready = 1;
 endmodule
 
-interface iface(input clk);
-    logic sel;
-    logic ready;
+interface iface (
+    input clk
+);
+  logic sel;
+  logic ready;
 endinterface
 
 class C_noinst;
-    virtual iface v;
-    int idx = 0;
+  virtual iface v;
+  int idx = 0;
 
-    task t_noinst();
-        forever begin
-            @(posedge v.clk);
-            if (v.ready && v.sel) begin
-            end
-        end
-    endtask
+  task t_noinst();
+    forever begin
+      @(posedge v.clk);
+      if (v.ready && v.sel) begin
+      end
+    end
+  endtask
 endclass
 
 module t;
-    logic clk;
-    iface i(.clk(clk));
+  logic clk;
+  iface i (.clk(clk));
 
-    leaf d(
-        .sel(i.sel),
-        .ready(i.ready)
-    );
+  leaf d (
+      .sel(i.sel),
+      .ready(i.ready)
+  );
 
-    initial #1 clk = ~clk;
+  initial #1 clk = ~clk;
 
-    initial #10 $finish;
+  initial #10 $finish;
 endmodule

test_regress/t/t_wait_iface_vif.v

@@ -3,9 +3,10 @@
 // This file ONLY is placed under the Creative Commons Public Domain.
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
-/* verilator lint_off ZERODLY */
 
-interface my_if();
+// verilator lint_off ZERODLY
+
+interface my_if ();
   logic clk;
   realtime clk_period;
   bit clk_active = 0;
@@ -52,7 +53,7 @@ class Driver;
 endclass
 
 module t;
-  my_if intf();
+  my_if intf ();
 
   // Verify combinational always with timing controls still works as coroutine
   int combo_timing_count = 0;