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Tests: Consolidate format specific t_trace_* tests (#7216) 

Factor out test execution into t/trace_*_common.py, which defines
a 'run' functions. All related t_trace_*py tests call this function.

Behaviour is partially encoded in the file name, which must be of the
form: t_trace_complex_<variant>_<mode>_<format>*.py, where '<variant>'
determines tracing options (default/params/structs), '<mode>' is the
compilation mode (--cc/--sc), and '<format>' determines the trace format
(vcd/fst/saif).

The part of the test name after '<format>' does not influence the test
directly and can be free form. If used, explicit 'verilator_flags2' is
passed to the 'run' function.
This commit is contained in:
Geza Lore 2026-03-12 15:21:02 +00:00 committed by GitHub
parent c74eee5123
commit 4b53f5f978
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
395 changed files with 16656 additions and 16108 deletions
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2
Makefile.in
View File

@ -577,7 +577,7 @@ MBAKE = mbake
MBAKE_FLAGS = format --config ./.bake.toml
format-exec:
-chmod a+x test_regress/t/*.py
-chmod a+x test_regress/t/t_*.py
-chmod a-x test_regress/t/*.v
format-make mbake:

28
include/verilated_saif_c.cpp
View File

@ -88,14 +88,15 @@ public:
class VerilatedSaifActivityVar final {
// MEMBERS
uint64_t m_lastTime = 0; // Last time when variable value was updated
uint64_t m_lastTime; // Last time when variable value was updated
VerilatedSaifActivityBit* m_bits; // Pointer to variable bits objects
uint32_t m_width; // Width of variable (in bits)
public:
// CONSTRUCTORS
VerilatedSaifActivityVar(uint32_t width, VerilatedSaifActivityBit* bits)
: m_bits{bits}
VerilatedSaifActivityVar(uint64_t startTime, uint32_t width, VerilatedSaifActivityBit* bits)
: m_lastTime{startTime}
, m_bits{bits}
, m_width{width} {}
VerilatedSaifActivityVar(VerilatedSaifActivityVar&&) = default;
@ -203,7 +204,7 @@ class VerilatedSaifActivityAccumulator final {
public:
// METHODS
void declare(uint32_t code, const std::string& absoluteScopePath, std::string variableName,
int bits, bool array, int arraynum);
int bits, bool array, int arraynum, uint64_t startTime);
// CONSTRUCTORS
VerilatedSaifActivityAccumulator() = default;
@ -252,7 +253,7 @@ VerilatedSaifActivityBit& VerilatedSaifActivityVar::bit(const std::size_t index)
void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string& absoluteScopePath,
std::string variableName, int bits, bool array,
int arraynum) {
int arraynum, uint64_t startTime) {
const size_t block_size = 1024;
if (m_activityArena.empty()
|| m_activityArena.back().size() + bits > m_activityArena.back().capacity()) {
@ -268,7 +269,7 @@ void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string&
variableName += ']';
}
m_scopeToActivities[absoluteScopePath].emplace_back(code, variableName);
m_activity.emplace(code, VerilatedSaifActivityVar{static_cast<uint32_t>(bits),
m_activity.emplace(code, VerilatedSaifActivityVar{startTime, static_cast<uint32_t>(bits),
m_activityArena.back().data() + bitsIdx});
}
@ -277,18 +278,18 @@ void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string&
//=============================================================================
// VerilatedSaif implementation
VerilatedSaif::VerilatedSaif(void* filep) {
m_activityAccumulators.emplace_back(std::make_unique<VerilatedSaifActivityAccumulator>());
}
VerilatedSaif::VerilatedSaif(void* filep) {}
void VerilatedSaif::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
const VerilatedLockGuard lock{m_mutex};
if (isOpen()) return;
m_startTime = currentTime();
m_filename = filename; // "" is ok, as someone may overload open
m_filep = ::open(m_filename.c_str(),
O_CREAT | O_WRONLY | O_TRUNC | O_LARGEFILE | O_NONBLOCK | O_CLOEXEC, 0666);
m_isOpen = true;
m_activityAccumulators.emplace_back(std::make_unique<VerilatedSaifActivityAccumulator>());
initializeSaifFileContents();
@ -328,7 +329,7 @@ void VerilatedSaif::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
void VerilatedSaif::finalizeSaifFileContents() {
printStr("(DURATION ");
printStr(std::to_string(currentTime()));
printStr(std::to_string(currentTime() - m_startTime));
printStr(")\n");
incrementIndent();
@ -419,7 +420,7 @@ bool VerilatedSaif::printActivityStats(VerilatedSaifActivityVar& activity,
// We only have two-value logic so TZ, TX and TB will always be 0
printStr(" (T0 ");
printStr(std::to_string(currentTime() - bit.highTime()));
printStr(std::to_string(currentTime() - m_startTime - bit.highTime()));
printStr(") (T1 ");
printStr(std::to_string(bit.highTime()));
printStr(") (TZ 0) (TX 0) (TB 0) (TC ");
@ -451,7 +452,8 @@ void VerilatedSaif::printStr(const std::string& str) {
void VerilatedSaif::writeBuffered(bool force) {
if (VL_UNLIKELY(m_buffer.size() >= WRITE_BUFFER_SIZE || force)) {
if (VL_UNLIKELY(!m_buffer.empty())) {
::write(m_filep, m_buffer.data(), m_buffer.size());
const ssize_t n = ::write(m_filep, m_buffer.data(), m_buffer.size());
assert(n == static_cast<ssize_t>(m_buffer.size()));
m_buffer = "";
m_buffer.reserve(WRITE_BUFFER_SIZE * 2);
}
@ -544,7 +546,7 @@ void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name
m_currentScope->addActivityVar(code, variableName);
accumulator.declare(code, m_currentScope->path(), std::move(variableName), bits, array,
arraynum);
arraynum, m_startTime);
}
// versions to call when the sig is not array member

1
include/verilated_saif_c.h
View File

@ -51,6 +51,7 @@ private:
int m_filep = 0; // File we're writing to
bool m_isOpen = false; // True indicates open file
uint64_t m_startTime = 0; // Time file was opened
std::string m_filename; // Filename we're writing to (if open)
std::string m_buffer; // Write data buffer

18
test_regress/driver.py
View File

@ -1697,6 +1697,13 @@ class VlTest:
self._ok = False
return self._ok
def parse_name(self, regex: str):
basename = os.path.basename(test.py_filename)
match = re.match(regex, basename.partition(".")[0])
if match is None:
test.error(f"Invalid test file name '{basename}")
return match.groups()
def passes(self, is_ok=True):
if not self.errors:
self._ok = is_ok
@ -2562,6 +2569,17 @@ class VlTest:
self.copy_if_golden(fn1, fn2)
self.error("SAIF files miscompare")
def trace_identical(self, traceFn: str, goldenFn: str, ignore_attr: bool = False) -> None:
match traceFn.rpartition(".")[-1]:
case "vcd":
self.vcd_identical(traceFn, goldenFn, ignore_attr)
case "fst":
self.fst_identical(traceFn, goldenFn, ignore_attr)
case "saif":
self.saif_identical(traceFn, goldenFn)
case _:
self.error("Unknown trace file format " + traceFn)
def _vcd_read(self, filename: str) -> dict:
data = {}
with open(filename, 'r', encoding='latin-1') as fh:

40
test_regress/t/t_hier_block_sc_trace_fst.py
View File

@ -1,40 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
test.clean_objs()
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# So use 6 threads here though it's not optimal in performance, but ok.
test.compile(v_flags2=['t/t_hier_block.cpp'],
verilator_flags2=[
'--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"',
"--CFLAGS", '"-O0 -ggdb"', "--trace-fst"
],
threads=(6 if test.vltmt else 1))
test.execute()
test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0")
test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1")
test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2")
test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14)
test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus")
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

40
test_regress/t/t_hier_block_sc_trace_vcd.py
View File

@ -1,40 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
test.clean_objs()
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# So use 6 threads here though it's not optimal in performance, but ok.
test.compile(v_flags2=['t/t_hier_block.cpp'],
verilator_flags2=[
'--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"',
"--CFLAGS", '"-O0 -ggdb"', "--trace-vcd"
],
threads=(6 if test.vltmt else 1))
test.execute()
test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0")
test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1")
test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2")
test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14)
test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus")
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

63
test_regress/t/t_hier_block_trace_fst.py
View File

@ -1,63 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
noinline = "noinl" in test.name
notop = "notop" in test.name
if not noinline and not notop:
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
verilator_common_flags = [
't/t_hier_block.cpp',
'--Wno-TIMESCALEMOD',
'--trace-fst',
'--trace-underscore', # Should not trace handle
"--trace-max-width",
"0",
"--trace-max-array",
"0",
"--trace-structs",
]
verilator_hier_flags = verilator_common_flags + ['--hierarchical']
if noinline:
verilator_hier_flags.extend(["+define+NO_INLINE"])
main_top_name = "top"
if notop:
main_top_name = ""
# Compile hierarchically
test.vm_prefix = "Vhier"
test.main_filename = test.obj_dir + "/Vhier__main.cpp"
test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
# Compile non-hierarchically
test.vm_prefix = "Vnonh"
test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
trace_hier = test.trace_filename.replace("simx", "hier")
trace_nonh = test.trace_filename.replace("simx", "nonh")
# Run the hierarchical model
test.execute(executable=test.obj_dir + "/Vhier")
test.run(cmd=["mv", test.trace_filename, trace_hier])
# Run the non-hierarchical model
test.execute(executable=test.obj_dir + "/Vnonh")
test.run(cmd=["mv", test.trace_filename, trace_nonh])
# The two models must match - ignore enum type attributes which can differ
test.fst_identical(trace_hier, trace_nonh, ignore_attr=True)
# The hierarchical must match the reference
test.fst_identical(trace_hier, test.golden_filename.replace("_noinl", ""))
test.passes()

63
test_regress/t/t_hier_block_trace_saif.py
View File

@ -1,63 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
noinline = "noinl" in test.name
notop = "notop" in test.name
if not noinline and not notop:
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
verilator_common_flags = [
't/t_hier_block.cpp',
'--Wno-TIMESCALEMOD',
'--trace-saif',
'--trace-underscore', # Should not trace handle
"--trace-max-width",
"0",
"--trace-max-array",
"0",
"--trace-structs",
]
verilator_hier_flags = verilator_common_flags + ['--hierarchical']
if noinline:
verilator_hier_flags.extend(["+define+NO_INLINE"])
main_top_name = "top"
if notop:
main_top_name = ""
# Compile hierarchically
test.vm_prefix = "Vhier"
test.main_filename = test.obj_dir + "/Vhier__main.cpp"
test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
# Compile non-hierarchically
test.vm_prefix = "Vnonh"
test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
trace_hier = test.trace_filename.replace("simx", "hier")
trace_nonh = test.trace_filename.replace("simx", "nonh")
# Run the hierarchical model
test.execute(executable=test.obj_dir + "/Vhier")
test.run(cmd=["mv", test.trace_filename, trace_hier])
# Run the non-hierarchical model
test.execute(executable=test.obj_dir + "/Vnonh")
test.run(cmd=["mv", test.trace_filename, trace_nonh])
# The two models must match
test.saif_identical(trace_hier, trace_nonh)
# The hierarchical must match the reference
test.saif_identical(trace_hier, test.golden_filename.replace("_noinl", ""))
test.passes()

77
test_regress/t/t_hier_block_trace_vcd.py
View File

@ -1,77 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import re
noinline = "noinl" in test.name
notop = "notop" in test.name
if not noinline and not notop:
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
verilator_common_flags = [
't/t_hier_block.cpp',
'--Wno-TIMESCALEMOD',
'--trace-vcd',
'--trace-underscore', # Should not trace handle
"--trace-max-width",
"0",
"--trace-max-array",
"0",
"--trace-structs",
]
verilator_hier_flags = verilator_common_flags + ['--hierarchical']
if noinline:
verilator_hier_flags.extend(["+define+NO_INLINE"])
main_top_name = "top"
if notop:
main_top_name = ""
# Compile hierarchically
test.vm_prefix = "Vhier"
test.main_filename = test.obj_dir + "/Vhier__main.cpp"
test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
# Compile non-hierarchically
test.vm_prefix = "Vnonh"
test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
trace_hier = test.trace_filename.replace("simx", "hier")
trace_nonh = test.trace_filename.replace("simx", "nonh")
# Run the hierarchical model
test.execute(executable=test.obj_dir + "/Vhier")
test.run(cmd=["mv", test.trace_filename, trace_hier])
# Run the non-hierarchical model
test.execute(executable=test.obj_dir + "/Vnonh")
test.run(cmd=["mv", test.trace_filename, trace_nonh])
# Scope structure must match exactly
with open(trace_nonh, 'r', encoding='utf8') as fnonh, open(trace_hier, 'r',
encoding='utf8') as fhier:
for la, lb in zip(fnonh, fhier):
la = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', la)
lb = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', lb)
if la != lb:
test.error_keep_going("VCD header mismatch: '{}' !~ '{}'".format(
la.strip(), lb.strip()))
if "enddefinitions" in la:
break
# The two models must match
test.vcd_identical(trace_hier, trace_nonh)
# The hierarchical must match the reference
test.vcd_identical(trace_hier, test.golden_filename.replace("_noinl", ""))
test.passes()

26
test_regress/t/t_hier_block_trace_vcd_statful_pkg.py
View File

@ -1,26 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.priority(30)
test.scenarios('vlt_all')
test.top_filename = "t/t_hier_block.v"
test.compile(verilator_flags2=[
't/t_hier_block.cpp', '--Wno-TIMESCALEMOD', '--trace-vcd', '--trace-underscore',
"--trace-max-width", "0", "--trace-max-array", "0", "--trace-structs", "--hierarchical",
"+define+STATEFUL_PKG"
])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_hier_trace.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=[
'--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t',
'--hierarchical', '-F t/t_hier_trace_sub/top.vc'
])
test.execute(all_run_flags=['-j 4'])
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_hier_trace_noinl.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_hier_trace.v"
test.compile(verilator_flags2=[
'--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t',
'--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.vc'
])
test.execute(all_run_flags=['-j 4'])
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

20
test_regress/t/t_interface_ref_trace.py
View File

@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--trace-structs --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/t_interface_ref_trace_fst.py
View File

@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.compile(verilator_flags2=['--trace-structs --trace-fst'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_interface_ref_trace_fst_sc.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--trace-structs --trace-fst --sc'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/t_interface_ref_trace_inla.py
View File

@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.golden_filename = "t/t_interface_ref_trace.out"
test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_interface_ref_trace_inlab.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.golden_filename = "t/t_interface_ref_trace.out"
test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'],
verilator_flags2=['--trace-structs --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/t_interface_ref_trace_inlb.py
View File

@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.golden_filename = "t/t_interface_ref_trace.out"
test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

674
test_regress/t/t_interface_ref_trace_noinl.out
View File

@ -1,674 +0,0 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$var wire 1 0 clk $end
$scope module t $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$scope module intf_1 $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$scope module intf_2 $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$scope module s1 $end
$scope module intf_for_struct $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module s2 $end
$scope module intf_for_struct $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module c1 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module c2 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module a $end
$scope module intf_one $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$scope module intf_two $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$scope module intf_in_sub_all $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 * value [31:0] $end
$scope module the_struct $end
$var wire 32 + val100 [31:0] $end
$var wire 32 , val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 3 value [31:0] $end
$upscope $end
$upscope $end
$scope module ac1 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope module intf_for_struct $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 * value [31:0] $end
$scope module the_struct $end
$var wire 32 + val100 [31:0] $end
$var wire 32 , val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 3 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 * value [31:0] $end
$scope module the_struct $end
$var wire 32 + val100 [31:0] $end
$var wire 32 , val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 3 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module abcdefghijklmnopqrstuvwxyz $end
$scope module intf_one $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$scope module intf_two $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$scope module intf_in_sub_all $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 - value [31:0] $end
$scope module the_struct $end
$var wire 32 . val100 [31:0] $end
$var wire 32 / val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 4 value [31:0] $end
$upscope $end
$upscope $end
$scope module ac1 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 ' value [31:0] $end
$scope module the_struct $end
$var wire 32 ( val100 [31:0] $end
$var wire 32 ) val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 $ value [31:0] $end
$scope module the_struct $end
$var wire 32 % val100 [31:0] $end
$var wire 32 & val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 1 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope module intf_for_struct $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 - value [31:0] $end
$scope module the_struct $end
$var wire 32 . val100 [31:0] $end
$var wire 32 / val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 4 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope module intf_for_check $end
$var wire 1 0 clk $end
$var wire 32 # cyc [31:0] $end
$var wire 32 - value [31:0] $end
$scope module the_struct $end
$var wire 32 . val100 [31:0] $end
$var wire 32 / val200 [31:0] $end
$upscope $end
$scope module inner $end
$var wire 32 # cyc [31:0] $end
$var wire 32 4 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b00000000000000000000000000000000 #
b00000000000000000000000000000001 $
b00000000000000000000000001100101 %
b00000000000000000000000011001001 &
b00000000000000000000000000000010 '
b00000000000000000000000001100110 (
b00000000000000000000000011001010 )
b00000000000000000000001111101001 *
b00000000000000000000010001001101 +
b00000000000000000000010010110001 ,
b00000000000000000000001111101010 -
b00000000000000000000010001001110 .
b00000000000000000000010010110010 /
00
b00000000000000000000000000000000 1
b00000000000000000000000000000000 2
b00000000000000000000000000000000 3
b00000000000000000000000000000000 4
#10
b00000000000000000000000000000001 #
b00000000000000000000000000000010 $
b00000000000000000000000001100110 %
b00000000000000000000000011001010 &
b00000000000000000000000000000011 '
b00000000000000000000000001100111 (
b00000000000000000000000011001011 )
b00000000000000000000001111101010 *
b00000000000000000000010001001110 +
b00000000000000000000010010110010 ,
b00000000000000000000001111101011 -
b00000000000000000000010001001111 .
b00000000000000000000010010110011 /
10
#15
00
#20
b00000000000000000000000000000010 #
b00000000000000000000000000000011 $
b00000000000000000000000001100111 %
b00000000000000000000000011001011 &
b00000000000000000000000000000100 '
b00000000000000000000000001101000 (
b00000000000000000000000011001100 )
b00000000000000000000001111101011 *
b00000000000000000000010001001111 +
b00000000000000000000010010110011 ,
b00000000000000000000001111101100 -
b00000000000000000000010001010000 .
b00000000000000000000010010110100 /
10
#25
00
#30
b00000000000000000000000000000011 #
b00000000000000000000000000000100 $
b00000000000000000000000001101000 %
b00000000000000000000000011001100 &
b00000000000000000000000000000101 '
b00000000000000000000000001101001 (
b00000000000000000000000011001101 )
b00000000000000000000001111101100 *
b00000000000000000000010001010000 +
b00000000000000000000010010110100 ,
b00000000000000000000001111101101 -
b00000000000000000000010001010001 .
b00000000000000000000010010110101 /
10
#35
00
#40
b00000000000000000000000000000100 #
b00000000000000000000000000000101 $
b00000000000000000000000001101001 %
b00000000000000000000000011001101 &
b00000000000000000000000000000110 '
b00000000000000000000000001101010 (
b00000000000000000000000011001110 )
b00000000000000000000001111101101 *
b00000000000000000000010001010001 +
b00000000000000000000010010110101 ,
b00000000000000000000001111101110 -
b00000000000000000000010001010010 .
b00000000000000000000010010110110 /
10
#45
00
#50
b00000000000000000000000000000101 #
b00000000000000000000000000000110 $
b00000000000000000000000001101010 %
b00000000000000000000000011001110 &
b00000000000000000000000000000111 '
b00000000000000000000000001101011 (
b00000000000000000000000011001111 )
b00000000000000000000001111101110 *
b00000000000000000000010001010010 +
b00000000000000000000010010110110 ,
b00000000000000000000001111101111 -
b00000000000000000000010001010011 .
b00000000000000000000010010110111 /
10
#55
00
#60
b00000000000000000000000000000110 #
b00000000000000000000000000000111 $
b00000000000000000000000001101011 %
b00000000000000000000000011001111 &
b00000000000000000000000000001000 '
b00000000000000000000000001101100 (
b00000000000000000000000011010000 )
b00000000000000000000001111101111 *
b00000000000000000000010001010011 +
b00000000000000000000010010110111 ,
b00000000000000000000001111110000 -
b00000000000000000000010001010100 .
b00000000000000000000010010111000 /
10
#65
00
#70
b00000000000000000000000000000111 #
b00000000000000000000000000001000 $
b00000000000000000000000001101100 %
b00000000000000000000000011010000 &
b00000000000000000000000000001001 '
b00000000000000000000000001101101 (
b00000000000000000000000011010001 )
b00000000000000000000001111110000 *
b00000000000000000000010001010100 +
b00000000000000000000010010111000 ,
b00000000000000000000001111110001 -
b00000000000000000000010001010101 .
b00000000000000000000010010111001 /
10
#75
00
#80
b00000000000000000000000000001000 #
b00000000000000000000000000001001 $
b00000000000000000000000001101101 %
b00000000000000000000000011010001 &
b00000000000000000000000000001010 '
b00000000000000000000000001101110 (
b00000000000000000000000011010010 )
b00000000000000000000001111110001 *
b00000000000000000000010001010101 +
b00000000000000000000010010111001 ,
b00000000000000000000001111110010 -
b00000000000000000000010001010110 .
b00000000000000000000010010111010 /
10
#85
00
#90
b00000000000000000000000000001001 #
b00000000000000000000000000001010 $
b00000000000000000000000001101110 %
b00000000000000000000000011010010 &
b00000000000000000000000000001011 '
b00000000000000000000000001101111 (
b00000000000000000000000011010011 )
b00000000000000000000001111110010 *
b00000000000000000000010001010110 +
b00000000000000000000010010111010 ,
b00000000000000000000001111110011 -
b00000000000000000000010001010111 .
b00000000000000000000010010111011 /
10
#95
00
#100
b00000000000000000000000000001010 #
b00000000000000000000000000001011 $
b00000000000000000000000001101111 %
b00000000000000000000000011010011 &
b00000000000000000000000000001100 '
b00000000000000000000000001110000 (
b00000000000000000000000011010100 )
b00000000000000000000001111110011 *
b00000000000000000000010001010111 +
b00000000000000000000010010111011 ,
b00000000000000000000001111110100 -
b00000000000000000000010001011000 .
b00000000000000000000010010111100 /
10
#105
00
#110
b00000000000000000000000000001011 #
b00000000000000000000000000001100 $
b00000000000000000000000001110000 %
b00000000000000000000000011010100 &
b00000000000000000000000000001101 '
b00000000000000000000000001110001 (
b00000000000000000000000011010101 )
b00000000000000000000001111110100 *
b00000000000000000000010001011000 +
b00000000000000000000010010111100 ,
b00000000000000000000001111110101 -
b00000000000000000000010001011001 .
b00000000000000000000010010111101 /
10
#115
00
#120
b00000000000000000000000000001100 #
b00000000000000000000000000001101 $
b00000000000000000000000001110001 %
b00000000000000000000000011010101 &
b00000000000000000000000000001110 '
b00000000000000000000000001110010 (
b00000000000000000000000011010110 )
b00000000000000000000001111110101 *
b00000000000000000000010001011001 +
b00000000000000000000010010111101 ,
b00000000000000000000001111110110 -
b00000000000000000000010001011010 .
b00000000000000000000010010111110 /
10
#125
00
#130
b00000000000000000000000000001101 #
b00000000000000000000000000001110 $
b00000000000000000000000001110010 %
b00000000000000000000000011010110 &
b00000000000000000000000000001111 '
b00000000000000000000000001110011 (
b00000000000000000000000011010111 )
b00000000000000000000001111110110 *
b00000000000000000000010001011010 +
b00000000000000000000010010111110 ,
b00000000000000000000001111110111 -
b00000000000000000000010001011011 .
b00000000000000000000010010111111 /
10
#135
00
#140
b00000000000000000000000000001110 #
b00000000000000000000000000001111 $
b00000000000000000000000001110011 %
b00000000000000000000000011010111 &
b00000000000000000000000000010000 '
b00000000000000000000000001110100 (
b00000000000000000000000011011000 )
b00000000000000000000001111110111 *
b00000000000000000000010001011011 +
b00000000000000000000010010111111 ,
b00000000000000000000001111111000 -
b00000000000000000000010001011100 .
b00000000000000000000010011000000 /
10
#145
00
#150
b00000000000000000000000000001111 #
b00000000000000000000000000010000 $
b00000000000000000000000001110100 %
b00000000000000000000000011011000 &
b00000000000000000000000000010001 '
b00000000000000000000000001110101 (
b00000000000000000000000011011001 )
b00000000000000000000001111111000 *
b00000000000000000000010001011100 +
b00000000000000000000010011000000 ,
b00000000000000000000001111111001 -
b00000000000000000000010001011101 .
b00000000000000000000010011000001 /
10
#155
00
#160
b00000000000000000000000000010000 #
b00000000000000000000000000010001 $
b00000000000000000000000001110101 %
b00000000000000000000000011011001 &
b00000000000000000000000000010010 '
b00000000000000000000000001110110 (
b00000000000000000000000011011010 )
b00000000000000000000001111111001 *
b00000000000000000000010001011101 +
b00000000000000000000010011000001 ,
b00000000000000000000001111111010 -
b00000000000000000000010001011110 .
b00000000000000000000010011000010 /
10
#165
00
#170
b00000000000000000000000000010001 #
b00000000000000000000000000010010 $
b00000000000000000000000001110110 %
b00000000000000000000000011011010 &
b00000000000000000000000000010011 '
b00000000000000000000000001110111 (
b00000000000000000000000011011011 )
b00000000000000000000001111111010 *
b00000000000000000000010001011110 +
b00000000000000000000010011000010 ,
b00000000000000000000001111111011 -
b00000000000000000000010001011111 .
b00000000000000000000010011000011 /
10
#175
00
#180
b00000000000000000000000000010010 #
b00000000000000000000000000010011 $
b00000000000000000000000001110111 %
b00000000000000000000000011011011 &
b00000000000000000000000000010100 '
b00000000000000000000000001111000 (
b00000000000000000000000011011100 )
b00000000000000000000001111111011 *
b00000000000000000000010001011111 +
b00000000000000000000010011000011 ,
b00000000000000000000001111111100 -
b00000000000000000000010001100000 .
b00000000000000000000010011000100 /
10
#185
00
#190
b00000000000000000000000000010011 #
b00000000000000000000000000010100 $
b00000000000000000000000001111000 %
b00000000000000000000000011011100 &
b00000000000000000000000000010101 '
b00000000000000000000000001111001 (
b00000000000000000000000011011101 )
b00000000000000000000001111111100 *
b00000000000000000000010001100000 +
b00000000000000000000010011000100 ,
b00000000000000000000001111111101 -
b00000000000000000000010001100001 .
b00000000000000000000010011000101 /
10
#195
00
#200
b00000000000000000000000000010100 #
b00000000000000000000000000010101 $
b00000000000000000000000001111001 %
b00000000000000000000000011011101 &
b00000000000000000000000000010110 '
b00000000000000000000000001111010 (
b00000000000000000000000011011110 )
b00000000000000000000001111111101 *
b00000000000000000000010001100001 +
b00000000000000000000010011000101 ,
b00000000000000000000001111111110 -
b00000000000000000000010001100010 .
b00000000000000000000010011000110 /
10
#205
00
#210
b00000000000000000000000000010101 #
b00000000000000000000000000010110 $
b00000000000000000000000001111010 %
b00000000000000000000000011011110 &
b00000000000000000000000000010111 '
b00000000000000000000000001111011 (
b00000000000000000000000011011111 )
b00000000000000000000001111111110 *
b00000000000000000000010001100010 +
b00000000000000000000010011000110 ,
b00000000000000000000001111111111 -
b00000000000000000000010001100011 .
b00000000000000000000010011000111 /
10

24
test_regress/t/t_interface_ref_trace_noinl.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
# Should be the same as the inlined version, but might have declarations
# in a different order. Sadly vcddiff can't check equivalence
# test.golden_filename = "t/t_interface_ref_trace.out"
test.compile(verilator_flags2=['-fno-inline --trace-structs --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

19
test_regress/t/t_interface_ref_trace_noinl_notrace.py
View File

@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.compile(verilator_flags2=['-fno-inline'])
test.execute()
test.passes()

22
test_regress/t/t_interface_ref_trace_saif.py
View File

@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.golden_filename = "t/t_interface_ref_trace_saif.out"
test.compile(verilator_flags2=['--trace-structs --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

5873
test_regress/t/t_no_trace_top.out
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File diff suppressed because it is too large Load Diff

20
test_regress/t/t_timing_trace.py
View File

@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary --trace-vcd -Wno-MINTYPMAXDLY"])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/t_timing_trace_fst.py
View File

@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_timing_trace.v"
test.compile(verilator_flags2=["--binary --trace-fst -Wno-MINTYPMAXDLY"])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

21
test_regress/t/t_timing_trace_saif.py
View File

@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_timing_trace.v"
test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

20
test_regress/t/t_trace_abort.py
View File

@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.compile(verilator_flags2=['--cc --trace-vcd'])
test.execute(fails=True)
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_abort_fst.out → test_regress/t/t_trace_abort_cc_fst.out
View File

15
test_regress/t/t_trace_abort_cc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_abort_common
test.scenarios('vlt_all')
trace_abort_common.run(test)

0
test_regress/t/t_trace_abort_saif.out → test_regress/t/t_trace_abort_cc_saif.out
View File

15
test_regress/t/t_trace_abort_cc_saif.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_abort_common
test.scenarios('vlt_all')
trace_abort_common.run(test)

0
test_regress/t/t_trace_abort.out → test_regress/t/t_trace_abort_cc_vcd.out
View File

15
test_regress/t/t_trace_abort_cc_vcd.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_abort_common
test.scenarios('vlt_all')
trace_abort_common.run(test)

21
test_regress/t/t_trace_abort_fst.py
View File

@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_abort.v"
test.compile(verilator_flags2=['--cc --trace-fst'])
test.execute(fails=True)
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_abort_fst_sc.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_abort.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-fst'])
test.execute(fails=True)
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

22
test_regress/t/t_trace_abort_saif.py
View File

@ -1,22 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_abort.v"
test.golden_filename = "t/t_trace_abort_saif.out"
test.compile(verilator_flags2=['--cc --trace-saif'])
test.execute(fails=True)
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_abort_fst_sc.out → test_regress/t/t_trace_abort_sc_fst.out
View File

15
test_regress/t/t_trace_abort_sc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_abort_common
test.scenarios('vlt_all')
trace_abort_common.run(test)

20
test_regress/t/t_trace_array.py
View File

@ -1,20 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --trace-max-width 0'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_array_fst.out → test_regress/t/t_trace_array_cc_fst.out
View File

15
test_regress/t/t_trace_array_cc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test)

15
test_regress/t/t_trace_array_cc_fst_portable.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"])

15
test_regress/t/t_trace_array_cc_fst_threads_1.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"])

15
test_regress/t/t_trace_array_cc_fst_threads_2.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "2"])

0
test_regress/t/t_trace_array_saif.out → test_regress/t/t_trace_array_cc_saif.out
View File

15
test_regress/t/t_trace_array_cc_saif.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test)

15
test_regress/t/t_trace_array_cc_saif_portable.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"])

15
test_regress/t/t_trace_array_cc_saif_threads_1.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"])

0
test_regress/t/t_trace_array.out → test_regress/t/t_trace_array_cc_vcd.out
View File

15
test_regress/t/t_trace_array_cc_vcd.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test)

15
test_regress/t/t_trace_array_cc_vcd_threads_1.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"])

21
test_regress/t/t_trace_array_fst.py
View File

@ -1,21 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_array_fst_portable.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(verilator_flags2=[
'--cc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

27
test_regress/t/t_trace_array_fst_portable_sc.py
View File

@ -1,27 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=[
'--sc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_array_fst_sc.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_trace_array_fst_threads_1.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(
verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

26
test_regress/t/t_trace_array_fst_threads_1_sc.py
View File

@ -1,26 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(
verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_trace_array_fst_threads_2.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst.out"
test.compile(
verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

26
test_regress/t/t_trace_array_fst_threads_2_sc.py
View File

@ -1,26 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_fst_sc.out"
if not test.have_sc:
test.skip("No SystemC installed")
test.compile(
verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0'])
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

23
test_regress/t/t_trace_array_saif.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_saif.out"
test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --trace-max-width 0'])
test.execute()
# saif_identical is very slow, so require exact match
test.files_identical(test.trace_filename, test.golden_filename)
test.passes()

26
test_regress/t/t_trace_array_saif_portable.py
View File

@ -1,26 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_saif.out"
# Don't pass --trace-max-width 0, we shrink the file intentionally
test.compile(verilator_flags2=[
'--cc --trace-saif --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
])
test.execute()
# saif_identical is very slow, so require exact match
test.files_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_array_saif_threads_1.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_saif.out"
test.compile(
verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs --trace-max-width 0'])
test.execute()
# saif_identical is very slow, so require exact match
test.files_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_array_saif_threads_2.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array_saif.out"
test.compile(
verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs --trace-max-width 0'])
test.execute()
# saif_identical is very slow, so require exact match
test.files_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_array_fst_sc.out → test_regress/t/t_trace_array_sc_fst.out
View File

15
test_regress/t/t_trace_array_sc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test)

15
test_regress/t/t_trace_array_sc_fst_portable.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"])

15
test_regress/t/t_trace_array_sc_fst_threads_1.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"])

15
test_regress/t/t_trace_array_sc_fst_threads_2.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_array_common
test.scenarios('vlt_all')
trace_array_common.run(test, verilator_flags2=["--trace-threads", "2"])

23
test_regress/t/t_trace_array_threads_1.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_trace_array.v"
test.golden_filename = "t/t_trace_array.out"
test.compile(
verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs --trace-max-width 0'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

24
test_regress/t/t_trace_ascendingrange.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--cc --trace-vcd --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_ascendingrange_fst.out → test_regress/t/t_trace_ascendingrange_cc_fst.out
View File

15
test_regress/t/t_trace_ascendingrange_cc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_ascendingrange_common
test.scenarios('vlt_all')
trace_ascendingrange_common.run(test)

0
test_regress/t/t_trace_ascendingrange_saif.out → test_regress/t/t_trace_ascendingrange_cc_saif.out
View File

15
test_regress/t/t_trace_ascendingrange_cc_saif.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_ascendingrange_common
test.scenarios('vlt_all')
trace_ascendingrange_common.run(test)

0
test_regress/t/t_trace_ascendingrange.out → test_regress/t/t_trace_ascendingrange_cc_vcd.out
View File

15
test_regress/t/t_trace_ascendingrange_cc_vcd.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_ascendingrange_common
test.scenarios('vlt_all')
trace_ascendingrange_common.run(test)

25
test_regress/t/t_trace_ascendingrange_fst.py
View File

@ -1,25 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ascendingrange.v"
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--cc --trace-fst --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

28
test_regress/t/t_trace_ascendingrange_fst_sc.py
View File

@ -1,28 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ascendingrange.v"
if not test.have_sc:
test.skip("No SystemC installed")
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--sc --trace-fst --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.fst_identical(test.trace_filename, test.golden_filename)
test.passes()

26
test_regress/t/t_trace_ascendingrange_saif.py
View File

@ -1,26 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2025 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ascendingrange.v"
test.golden_filename = "t/t_trace_ascendingrange_saif.out"
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
# Strangely, asking for more threads makes it go away.
test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'],
threads=(6 if test.vltmt else 1))
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

0
test_regress/t/t_trace_ascendingrange_fst_sc.out → test_regress/t/t_trace_ascendingrange_sc_fst.out
View File

15
test_regress/t/t_trace_ascendingrange_sc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_ascendingrange_common
test.scenarios('vlt_all')
trace_ascendingrange_common.run(test)

21
test_regress/t/t_trace_fst.v → test_regress/t/t_trace_basic.v
View File

@ -4,20 +4,26 @@
// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin <johnjohnlys@media.ee.ntu.edu.tw>
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Outputs
state,
// Inouts
fst_inout,
// Inputs
module t (
clk
`ifndef SYSTEMC
,fst_inout
,state
`endif
);
input clk;
`ifndef SYSTEMC
output state;
inout fst_inout;
`endif
wire clk;
wire [4:0] state;
wire fst_inout;
int cyc;
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
@ -45,7 +51,6 @@ module t ( /*AUTOARG*/
wor fst_wor;
wire fst_wire;
uwire fst_uwire;
inout fst_inout;
Test test ( /*AUTOINST*/
// Outputs

6
test_regress/t/t_trace_fst.out → test_regress/t/t_trace_basic_cc_fst.out
View File

@ -1,5 +1,5 @@
$date
Tue Feb 17 01:32:42 2026
Thu Mar 12 09:10:51 2026
$end
$version
@ -14,9 +14,10 @@ $var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$var int 32 $ cyc [31:0] $end
$var logic 1 % rstn $end
$var wire 5 " state [4:0] $end
$var real_parameter 64 & fst_gparam_real $end
$var real_parameter 64 ' fst_lparam_real $end
$var real 64 & fst_real $end
@ -41,7 +42,6 @@ $var triand 1 6 fst_wand $end
$var trior 1 7 fst_wor $end
$var wire 1 8 fst_wire $end
$var wire 1 9 fst_uwire $end
$var wire 1 # fst_inout $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 % rstn $end

15
test_regress/t/t_trace_basic_cc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_cc_fst_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

12
test_regress/t/t_trace_saif.out → test_regress/t/t_trace_basic_cc_saif.out
View File

@ -19,6 +19,12 @@
(INSTANCE t
(NET
(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
@ -52,11 +58,6 @@
(cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@ -542,7 +543,6 @@
(fst_wor (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_uwire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
)
(INSTANCE test
(NET

15
test_regress/t/t_trace_basic_cc_saif.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_cc_saif_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

1124
test_regress/t/t_trace_basic_cc_vcd.out Normal file
View File

File diff suppressed because it is too large Load Diff

15
test_regress/t/t_trace_basic_cc_vcd.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_cc_vcd_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

1131
test_regress/t/t_trace_basic_sc_fst.out Normal file
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File diff suppressed because it is too large Load Diff

15
test_regress/t/t_trace_basic_sc_fst.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_sc_fst_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

80
test_regress/t/t_trace_saif_sc.out → test_regress/t/t_trace_basic_sc_saif.out
View File

@ -10,6 +10,12 @@
(INSTANCE t
(NET
(clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199))
(state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
(state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
(fst_inout (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(cyc\[0\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(cyc\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(cyc\[2\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 25))
@ -389,6 +395,70 @@
(fst_byte\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_byte\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_byte\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(fst_time\[2\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(fst_time\[3\] (T0 500) (T1 504) (TZ 0) (TX 0) (TB 0) (TC 75))
(fst_time\[4\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62))
(fst_time\[5\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 31))
(fst_time\[6\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 15))
(fst_time\[7\] (T0 510) (T1 494) (TZ 0) (TX 0) (TB 0) (TC 7))
(fst_time\[8\] (T0 510) (T1 494) (TZ 0) (TX 0) (TB 0) (TC 3))
(fst_time\[9\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_time\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_parameter\[0\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter\[1\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@ -458,12 +528,12 @@
(fst_tri0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_tri1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_tri (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_triand (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_trior (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_wand (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_wor (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_wire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
(state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
(fst_uwire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
)
(INSTANCE test
(NET

15
test_regress/t/t_trace_basic_sc_saif.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_sc_saif_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

1123
test_regress/t/t_trace_basic_sc_vcd.out Normal file
View File

File diff suppressed because it is too large Load Diff

15
test_regress/t/t_trace_basic_sc_vcd.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test)

15
test_regress/t/t_trace_basic_sc_vcd_cmake.py Executable file
View File

@ -0,0 +1,15 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_basic_common
test.scenarios('vlt_all')
trace_basic_common.run(test, cmake=True)

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