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Verilog format

This commit is contained in:
Veripool API Bot 2026-01-05 22:59:11 -05:00 committed by Wilson Snyder
parent 5efea48358
commit ff73e117e6
3 changed files with 73 additions and 67 deletions
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84
test_regress/t/t_interface_array_parameter_aggregate_access.v
View File

@ -5,57 +5,61 @@
// SPDX-License-Identifier: CC0-1.0
typedef struct {
int BAR_INT;
bit BAR_BIT;
byte BAR_ARRAY [0:3];
int BAR_INT;
bit BAR_BIT;
byte BAR_ARRAY[0:3];
} foo_t;
interface intf
#(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}})
(input wire clk,
input wire rst);
modport modp (input clk, rst);
interface intf #(
parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}
) (
input wire clk,
input wire rst
);
modport modp(input clk, rst);
endinterface
module sub (intf.modp the_intf_port [4], intf.modp single_intf_port);
localparam foo_t intf_foo = the_intf_port[0].FOO;
localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT;
localparam bit intf_foo_bar_bit = the_intf_port[0].FOO.BAR_BIT;
localparam byte intf_foo_bar_byte = the_intf_port[0].FOO.BAR_ARRAY[3];
localparam foo_t single_foo = single_intf_port.FOO;
localparam int single_foo_bar_int = single_intf_port.FOO.BAR_INT;
localparam bit single_foo_bar_bit = single_intf_port.FOO.BAR_BIT;
localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3];
module sub (
intf.modp the_intf_port[4],
intf.modp single_intf_port
);
localparam foo_t intf_foo = the_intf_port[0].FOO;
localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT;
localparam bit intf_foo_bar_bit = the_intf_port[0].FOO.BAR_BIT;
localparam byte intf_foo_bar_byte = the_intf_port[0].FOO.BAR_ARRAY[3];
localparam foo_t single_foo = single_intf_port.FOO;
localparam int single_foo_bar_int = single_intf_port.FOO.BAR_INT;
localparam bit single_foo_bar_bit = single_intf_port.FOO.BAR_BIT;
localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3];
initial begin
if (intf_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
if (intf_foo_bar_int != 4) $stop;
if (intf_foo_bar_bit != 1'b1) $stop;
if (intf_foo_bar_byte != 8'd8) $stop;
if (single_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
if (single_foo_bar_int != 4) $stop;
if (single_foo_bar_bit != 1'b1) $stop;
if (single_foo_bar_byte != 8'd8) $stop;
end
initial begin
if (intf_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
if (intf_foo_bar_int != 4) $stop;
if (intf_foo_bar_bit != 1'b1) $stop;
if (intf_foo_bar_byte != 8'd8) $stop;
if (single_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop;
if (single_foo_bar_int != 4) $stop;
if (single_foo_bar_bit != 1'b1) $stop;
if (single_foo_bar_byte != 8'd8) $stop;
end
endmodule
module t (
clk
);
logic rst;
input clk;
logic rst;
input clk;
intf the_intf [4] (.*);
intf single_intf (.*);
intf the_intf[4] (.*);
intf single_intf (.*);
sub
the_sub (
.the_intf_port (the_intf),
.single_intf_port(single_intf)
);
sub the_sub (
.the_intf_port(the_intf),
.single_intf_port(single_intf)
);
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

2
test_regress/t/t_randomize_arraysel_membersel.v
View File

@ -21,7 +21,7 @@ endclass
module t;
initial begin
test_class example;
example = new;
example = new;
example.b = new;
// Simple array element access

54
test_regress/t/t_randomize_module_var.v
View File

@ -6,38 +6,40 @@
module t_randomize_module_var;
int golden_queue[$];
int golden_queue[$];
class Cls;
rand bit deq;
constraint valid_enq {
if (golden_queue.size() == 0) {deq == 0;}
class Cls;
rand bit deq;
constraint valid_enq {
if (golden_queue.size() == 0) {
deq == 0;
}
endclass
}
endclass
Cls tr;
Cls tr;
initial begin
tr = new;
initial begin
tr = new;
// Test 1: Empty queue - deq must be 0
if (tr.randomize() == 0) begin
$stop;
end
if (tr.deq != 0) begin
$display("Error: Expected deq=0 when queue is empty, got %0d", tr.deq);
$stop;
end
// Test 1: Empty queue - deq must be 0
if (tr.randomize() == 0) begin
$stop;
end
if (tr.deq != 0) begin
$display("Error: Expected deq=0 when queue is empty, got %0d", tr.deq);
$stop;
end
// Test 2: Non-empty queue - deq can be 0 or 1
golden_queue.push_back(42);
if (tr.randomize() == 0) begin
$stop;
end
// deq can be 0 or 1, both are valid
// Test 2: Non-empty queue - deq can be 0 or 1
golden_queue.push_back(42);
if (tr.randomize() == 0) begin
$stop;
end
// deq can be 0 or 1, both are valid
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule