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Tests: Verilog format

This commit is contained in:
Veripool API Bot 2026-03-08 18:26:40 -04:00 committed by Wilson Snyder
parent 9c5f4e2483
commit 07ed6aef53
1130 changed files with 51974 additions and 51462 deletions
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32
test_regress/t/t_case_66bits.v
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@ -4,24 +4,22 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg [65:0] idx /*verilator public*/;
initial idx = 1;
reg [65:0] idx /*verilator public*/; initial idx = 1;
always @(posedge clk) begin
case(idx)
1: idx = 100;
100: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: $stop;
endcase
end
always @(posedge clk) begin
case (idx)
1: idx = 100;
100: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: $stop;
endcase
end
endmodule

128
test_regress/t/t_case_auto1.v
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@ -4,73 +4,73 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
// verilog_format: off
localparam // synopsys enum En_State
EP_State_IDLE = {3'b000,5'd00},
EP_State_CMDSHIFT0 = {3'b001,5'd00},
EP_State_CMDSHIFT13 = {3'b001,5'd13},
EP_State_CMDSHIFT14 = {3'b001,5'd14},
EP_State_CMDSHIFT15 = {3'b001,5'd15},
EP_State_CMDSHIFT16 = {3'b001,5'd16},
EP_State_DWAIT = {3'b010,5'd00},
EP_State_DSHIFT0 = {3'b100,5'd00},
EP_State_DSHIFT1 = {3'b100,5'd01},
EP_State_DSHIFT15 = {3'b100,5'd15};
localparam // synopsys enum En_State
EP_State_IDLE = {3'b000,5'd00},
EP_State_CMDSHIFT0 = {3'b001,5'd00},
EP_State_CMDSHIFT13 = {3'b001,5'd13},
EP_State_CMDSHIFT14 = {3'b001,5'd14},
EP_State_CMDSHIFT15 = {3'b001,5'd15},
EP_State_CMDSHIFT16 = {3'b001,5'd16},
EP_State_DWAIT = {3'b010,5'd00},
EP_State_DSHIFT0 = {3'b100,5'd00},
EP_State_DSHIFT1 = {3'b100,5'd01},
EP_State_DSHIFT15 = {3'b100,5'd15};
reg [7:0] /* synopsys enum En_State */
m_state_xr; // Last command, for debugging
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
// verilog_format: on
reg [7:0] /* synopsys enum En_State */
m_state_xr; // Last command, for debugging
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
integer cyc;
initial cyc = 1;
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc == 1) begin
m_state_xr <= EP_State_IDLE;
end
end
if (cyc == 2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
end
if (cyc == 3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
end
if (cyc == 4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
end
if (cyc == 9) begin
if (m_stateAscii_xr != "dwait ") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

6
test_regress/t/t_case_call_count.v
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@ -8,12 +8,12 @@ class Cls;
int callCount = 0;
int callCount2 = 0;
int value = 6;
bit[5:0] value2 = 6;
bit [5:0] value2 = 6;
function int get();
callCount += 1;
return value;
endfunction
function bit[5:0] get2();
function bit [5:0] get2();
callCount2 += 1;
return value2;
endfunction
@ -45,7 +45,7 @@ module t;
default: $stop;
endcase
case (c.getPure())
1:;
1: ;
default: $stop;
endcase
if (!called) $stop;

564
test_regress/t/t_case_deep.v
View File

@ -4,90 +4,92 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [33:0] in = crc[33:0];
// Take CRC data and apply to testblock inputs
wire [33:0] in = crc[33:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] code; // From test of Test.v
wire [4:0] len; // From test of Test.v
wire next; // From test of Test.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] code; // From test of Test.v
wire [4:0] len; // From test of Test.v
wire next; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.next (next),
.code (code[31:0]),
.len (len[4:0]),
// Inputs
.clk (clk),
.in (in[33:0]));
Test test ( /*AUTOINST*/
// Outputs
.next(next),
.code(code[31:0]),
.len(len[4:0]),
// Inputs
.clk(clk),
.in(in[33:0])
);
// Aggregate outputs into a single result vector
wire [63:0] result = {26'h0, next, len, code};
// Aggregate outputs into a single result vector
wire [63:0] result = {26'h0, next, len, code};
// What checksum will we end up with
`define EXPECTED_SUM 64'h5537fa30d49bf865
// What checksum will we end up with
`define EXPECTED_SUM 64'h5537fa30d49bf865
// Test loop
always @ (posedge clk) begin
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
next, code, len,
// Inputs
clk, in
);
module Test ( /*AUTOARG*/
// Outputs
next,
code,
len,
// Inputs
clk,
in
);
input clk;
input [33:0] in;
output next;
output [31:0] code;
output [4:0] len;
input clk;
input [33:0] in;
output next;
output [31:0] code;
output [4:0] len;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] code;
reg [4:0] len;
reg next;
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] code;
reg [4:0] len;
reg next;
// End of automatics
/*
/*
#!/usr/bin/env perl
use warnings;
srand(5);
@ -128,216 +130,216 @@ pat:
}
*/
always @* begin
next = 1'b0;
code = 32'd0;
len = 5'b11111;
casez (in[31:8])
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
24'b000000??????????????????: begin
casez (in[33:32])
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
default: ;
endcase
end
default: ;
endcase
end
always @* begin
next = 1'b0;
code = 32'd0;
len = 5'b11111;
casez (in[31:8])
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
24'b000000??????????????????: begin
casez (in[33:32])
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
default: ;
endcase
end
default: ;
endcase
end
endmodule

6
test_regress/t/t_case_default_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement.
16 | default: $stop;
| ^~~~~~~
%Error: t/t_case_default_bad.v:16:7: Multiple default statements in case statement.
16 | default: $stop;
| ^~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

24
test_regress/t/t_case_default_bad.v
View File

@ -4,16 +4,16 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
value
);
input [3:0] value;
always @ (/*AS*/value) begin
case (value)
default: $stop;
4'd0000: $stop;
default: $stop;
endcase
end
module t ( /*AUTOARG*/
// Inputs
value
);
input [3:0] value;
always @( /*AS*/ value) begin
case (value)
default: $stop;
4'd0000: $stop;
default: $stop;
endcase
end
endmodule

123
test_regress/t/t_case_dupitems.v
View File

@ -4,78 +4,77 @@
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
Test test ( /*AUTOINST*/
// Outputs
.out(out[1:0]),
// Inputs
.in(in[1:0])
);
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
module Test ( /*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule

30
test_regress/t/t_case_enum_complete.v
View File

@ -6,20 +6,24 @@
module t;
enum logic [2:0] {S0, S1, S2} state;
enum logic [2:0] {
S0,
S1,
S2
} state;
int v = 0;
int v = 0;
initial begin
state = S1;
initial begin
state = S1;
unique case (state)
S0, S2: $stop;
S1: v++;
endcase
unique case (state)
S2: $stop;
default: v++;
endcase
end
unique case (state)
S0, S2: $stop;
S1: v++;
endcase
unique case (state)
S2: $stop;
default: v++;
endcase
end
endmodule

114
test_regress/t/t_case_enum_complete_wildcard.v
View File

@ -8,67 +8,67 @@
module t;
enum logic [1:0] {
S00 = 'b00,
S01 = 'b01,
S10 = 'b10,
enum logic [1:0] {
S00 = 'b00,
S01 = 'b01,
S10 = 'b10,
S0X = 2'b0?,
SX0 = 2'b?0
} state;
S0X = 2'b0?,
SX0 = 2'b?0
} state;
int v = 0;
int v = 0;
initial begin
state = S01;
unique case (state)
S00: $stop;
S01: v++;
S10: $stop;
endcase
unique case (state)
S00: $stop;
default: v++; // default
endcase
unique case (state)
2'd0: $stop;
2'd1: v++;
2'd2: $stop;
endcase
unique case (state)
2'd0: $stop;
2'd1: v++;
2'd2: $stop;
2'd3: $stop; // extra case
endcase
initial begin
state = S01;
unique case (state)
S00: $stop;
S01: v++;
S10: $stop;
endcase
unique case (state)
S00: $stop;
default: v++; // default
endcase
unique case (state)
2'd0: $stop;
2'd1: v++;
2'd2: $stop;
endcase
unique case (state)
2'd0: $stop;
2'd1: v++;
2'd2: $stop;
2'd3: $stop; // extra case
endcase
unique case (state) inside
2'd0: $stop;
2'd1: v++;
[2'd2:2'd3]: $stop;
endcase
unique case (state) inside
[S00:S10]: v++;
endcase
unique case (state) inside
2'd0: $stop;
2'd1: v++;
[2'd2 : 2'd3]: $stop;
endcase
unique case (state) inside
[S00 : S10]: v++;
endcase
unique casez (state)
S10: $stop;
S0X: v++; // fully covered
endcase
unique casez (state)
S10: $stop;
S0X: v++;
2'b11: $stop; // extra case
endcase
unique casez (state)
S0X: v++;
default: $stop;
endcase
unique casez (state)
S10: $stop;
S0X: v++; // fully covered
endcase
unique casez (state)
S10: $stop;
S0X: v++;
2'b11: $stop; // extra case
endcase
unique casez (state)
S0X: v++;
default: $stop;
endcase
case (state)
S00: $stop;
S01: v++;
S10, 2'b11: $stop;
endcase
end
case (state)
S00: $stop;
S01: v++;
S10, 2'b11: $stop;
endcase
end
endmodule

32
test_regress/t/t_case_enum_emptyish.v
View File

@ -6,24 +6,24 @@
module t;
enum logic [2:0] {
e0,
e1,
e2,
e3
} EN;
enum logic [2:0] {
e0,
e1,
e2,
e3
} EN;
initial begin
initial begin
unique case (EN)
e0 :;
e1 :;
e2 :;
e3 :;
endcase
unique case (EN)
e0: ;
e1: ;
e2: ;
e3: ;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_case_enum_incomplete_bad.out
View File

@ -1,6 +1,6 @@
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:14:14: Enum item 'S1' not covered by case
14 | unique case (state)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:18:12: Enum item 'S1' not covered by case
18 | unique case (state)
| ^~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Error: Exiting due to

20
test_regress/t/t_case_enum_incomplete_bad.v
View File

@ -6,14 +6,18 @@
module t;
enum logic [2:0] {S0, S1, S2} state;
enum logic [2:0] {
S0,
S1,
S2
} state;
initial begin
state = S1;
initial begin
state = S1;
unique case (state)
S0: $stop;
S2: $stop;
endcase
end
unique case (state)
S0: $stop;
S2: $stop;
endcase
end
endmodule

24
test_regress/t/t_case_enum_incomplete_wildcard_bad.out
View File

@ -1,15 +1,15 @@
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:26:16: Enum item 'S10' not covered by case
26 | unique case (state)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:26:12: Enum item 'S10' not covered by case
26 | unique case (state)
| ^~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:30:16: Enum item 'S00' not covered by case
30 | unique case (state)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:35:16: Enum item 'S10' not covered by case
35 | unique casez (state)
| ^~~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:40:9: Case values incompletely covered (example pattern 0x3)
40 | case (state)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:30:12: Enum item 'S00' not covered by case
30 | unique case (state)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:35:12: Enum item 'S10' not covered by case
35 | unique casez (state)
| ^~~~~
%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:40:5: Case values incompletely covered (example pattern 0x3)
40 | case (state)
| ^~~~
%Error: Exiting due to

58
test_regress/t/t_case_enum_incomplete_wildcard_bad.v
View File

@ -5,42 +5,42 @@
// SPDX-License-Identifier: CC0-1.0
module t;
t1 i_t1();
t1 i_t1 ();
endmodule
module t1;
enum logic [1:0] {
S00 = 'b00,
S01 = 'b01,
S10 = 'b10,
enum logic [1:0] {
S00 = 'b00,
S01 = 'b01,
S10 = 'b10,
SX0 = 2'b?0,
S0X = 'b0?
} state;
SX0 = 2'b?0,
S0X = 'b0?
} state;
int v = 0;
int v = 0;
initial begin
state = S10;
unique case (state)
S00: $stop;
2'b01: $stop;
endcase
unique case (state)
2'd2: v++;
2'd1: $stop;
endcase
initial begin
state = S10;
unique case (state)
S00: $stop;
2'b01: $stop;
endcase
unique case (state)
2'd2: v++;
2'd1: $stop;
endcase
unique casez (state)
S0X: $stop;
2'b11: $stop;
endcase
unique casez (state)
S0X: $stop;
2'b11: $stop;
endcase
case (state)
S00: $stop;
S01: $stop;
S10: v++;
endcase
end
case (state)
S00: $stop;
S01: $stop;
S10: v++;
endcase
end
endmodule

30
test_regress/t/t_case_group.v
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@ -4,23 +4,21 @@
// SPDX-FileCopyrightText: 2014 Jonathon Donaldson
// SPDX-License-Identifier: CC0-1.0
module t
(
input i_clk,
input [6:0] i_input,
output logic o_output
);
module t (
input i_clk,
input [6:0] i_input,
output logic o_output
);
always_ff @(posedge i_clk)
// verilator lint_off CASEINCOMPLETE
case (i_input)
7'(92+2),
7'(92+3): o_output <= 1'b1;
endcase
always_ff @(posedge i_clk)
// verilator lint_off CASEINCOMPLETE
case (i_input)
7'(92 + 2), 7'(92 + 3): o_output <= 1'b1;
endcase
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

373
test_regress/t/t_case_huge.v
View File

@ -4,207 +4,208 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
input clk;
reg [9:0] index;
wire [7:0] index0 = index[7:0] + 8'h0;
wire [7:0] index1 = index[7:0] + 8'h1;
wire [7:0] index2 = index[7:0] + 8'h2;
wire [7:0] index3 = index[7:0] + 8'h3;
wire [7:0] index4 = index[7:0] + 8'h4;
wire [7:0] index5 = index[7:0] + 8'h5;
wire [7:0] index6 = index[7:0] + 8'h6;
wire [7:0] index7 = index[7:0] + 8'h7;
reg [9:0] index;
wire [7:0] index0 = index[7:0] + 8'h0;
wire [7:0] index1 = index[7:0] + 8'h1;
wire [7:0] index2 = index[7:0] + 8'h2;
wire [7:0] index3 = index[7:0] + 8'h3;
wire [7:0] index4 = index[7:0] + 8'h4;
wire [7:0] index5 = index[7:0] + 8'h5;
wire [7:0] index6 = index[7:0] + 8'h6;
wire [7:0] index7 = index[7:0] + 8'h7;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] outa0; // From s0 of t_case_huge_sub.v
wire [9:0] outa1; // From s1 of t_case_huge_sub.v
wire [9:0] outa2; // From s2 of t_case_huge_sub.v
wire [9:0] outa3; // From s3 of t_case_huge_sub.v
wire [9:0] outa4; // From s4 of t_case_huge_sub.v
wire [9:0] outa5; // From s5 of t_case_huge_sub.v
wire [9:0] outa6; // From s6 of t_case_huge_sub.v
wire [9:0] outa7; // From s7 of t_case_huge_sub.v
wire [1:0] outb0; // From s0 of t_case_huge_sub.v
wire [1:0] outb1; // From s1 of t_case_huge_sub.v
wire [1:0] outb2; // From s2 of t_case_huge_sub.v
wire [1:0] outb3; // From s3 of t_case_huge_sub.v
wire [1:0] outb4; // From s4 of t_case_huge_sub.v
wire [1:0] outb5; // From s5 of t_case_huge_sub.v
wire [1:0] outb6; // From s6 of t_case_huge_sub.v
wire [1:0] outb7; // From s7 of t_case_huge_sub.v
wire outc0; // From s0 of t_case_huge_sub.v
wire outc1; // From s1 of t_case_huge_sub.v
wire outc2; // From s2 of t_case_huge_sub.v
wire outc3; // From s3 of t_case_huge_sub.v
wire outc4; // From s4 of t_case_huge_sub.v
wire outc5; // From s5 of t_case_huge_sub.v
wire outc6; // From s6 of t_case_huge_sub.v
wire outc7; // From s7 of t_case_huge_sub.v
wire [9:0] outq; // From q of t_case_huge_sub4.v
wire [3:0] outr; // From sub3 of t_case_huge_sub3.v
wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [9:0] outa0; // From s0 of t_case_huge_sub.v
logic [9:0] outa1; // From s1 of t_case_huge_sub.v
logic [9:0] outa2; // From s2 of t_case_huge_sub.v
logic [9:0] outa3; // From s3 of t_case_huge_sub.v
logic [9:0] outa4; // From s4 of t_case_huge_sub.v
logic [9:0] outa5; // From s5 of t_case_huge_sub.v
logic [9:0] outa6; // From s6 of t_case_huge_sub.v
logic [9:0] outa7; // From s7 of t_case_huge_sub.v
logic [1:0] outb0; // From s0 of t_case_huge_sub.v
logic [1:0] outb1; // From s1 of t_case_huge_sub.v
logic [1:0] outb2; // From s2 of t_case_huge_sub.v
logic [1:0] outb3; // From s3 of t_case_huge_sub.v
logic [1:0] outb4; // From s4 of t_case_huge_sub.v
logic [1:0] outb5; // From s5 of t_case_huge_sub.v
logic [1:0] outb6; // From s6 of t_case_huge_sub.v
logic [1:0] outb7; // From s7 of t_case_huge_sub.v
logic outc0; // From s0 of t_case_huge_sub.v
logic outc1; // From s1 of t_case_huge_sub.v
logic outc2; // From s2 of t_case_huge_sub.v
logic outc3; // From s3 of t_case_huge_sub.v
logic outc4; // From s4 of t_case_huge_sub.v
logic outc5; // From s5 of t_case_huge_sub.v
logic outc6; // From s6 of t_case_huge_sub.v
logic outc7; // From s7 of t_case_huge_sub.v
logic [9:0] outq; // From q of t_case_huge_sub4.v
logic [3:0] outr; // From sub3 of t_case_huge_sub3.v
logic [9:0] outsmall; // From sub2 of t_case_huge_sub2.v
// End of automatics
t_case_huge_sub2 sub2 (
// Outputs
.outa (outsmall[9:0]),
/*AUTOINST*/
// Inputs
.index (index[9:0]));
t_case_huge_sub2 sub2 (
// Outputs
.outa(outsmall[9:0]),
/*AUTOINST*/
// Inputs
.index (index[9:0]));
t_case_huge_sub3 sub3 (/*AUTOINST*/
// Outputs
.outr (outr[3:0]),
// Inputs
.clk (clk),
.index (index[9:0]));
t_case_huge_sub3 sub3 ( /*AUTOINST*/
// Outputs
.outr (outr[3:0]),
// Inputs
.clk (clk),
.index (index[9:0]));
/* t_case_huge_sub AUTO_TEMPLATE (
/* t_case_huge_sub AUTO_TEMPLATE (
.outa (outa@[]),
.outb (outb@[]),
.outc (outc@[]),
.index (index@[]));
*/
t_case_huge_sub s0 (/*AUTOINST*/
// Outputs
.outa (outa0[9:0]), // Templated
.outb (outb0[1:0]), // Templated
.outc (outc0), // Templated
// Inputs
.index (index0[7:0])); // Templated
t_case_huge_sub s1 (/*AUTOINST*/
// Outputs
.outa (outa1[9:0]), // Templated
.outb (outb1[1:0]), // Templated
.outc (outc1), // Templated
// Inputs
.index (index1[7:0])); // Templated
t_case_huge_sub s2 (/*AUTOINST*/
// Outputs
.outa (outa2[9:0]), // Templated
.outb (outb2[1:0]), // Templated
.outc (outc2), // Templated
// Inputs
.index (index2[7:0])); // Templated
t_case_huge_sub s3 (/*AUTOINST*/
// Outputs
.outa (outa3[9:0]), // Templated
.outb (outb3[1:0]), // Templated
.outc (outc3), // Templated
// Inputs
.index (index3[7:0])); // Templated
t_case_huge_sub s4 (/*AUTOINST*/
// Outputs
.outa (outa4[9:0]), // Templated
.outb (outb4[1:0]), // Templated
.outc (outc4), // Templated
// Inputs
.index (index4[7:0])); // Templated
t_case_huge_sub s5 (/*AUTOINST*/
// Outputs
.outa (outa5[9:0]), // Templated
.outb (outb5[1:0]), // Templated
.outc (outc5), // Templated
// Inputs
.index (index5[7:0])); // Templated
t_case_huge_sub s6 (/*AUTOINST*/
// Outputs
.outa (outa6[9:0]), // Templated
.outb (outb6[1:0]), // Templated
.outc (outc6), // Templated
// Inputs
.index (index6[7:0])); // Templated
t_case_huge_sub s7 (/*AUTOINST*/
// Outputs
.outa (outa7[9:0]), // Templated
.outb (outb7[1:0]), // Templated
.outc (outc7), // Templated
// Inputs
.index (index7[7:0])); // Templated
t_case_huge_sub s0 ( /*AUTOINST*/
// Outputs
.outa (outa0[9:0]), // Templated
.outb (outb0[1:0]), // Templated
.outc (outc0), // Templated
// Inputs
.index (index0[7:0])); // Templated
t_case_huge_sub s1 ( /*AUTOINST*/
// Outputs
.outa (outa1[9:0]), // Templated
.outb (outb1[1:0]), // Templated
.outc (outc1), // Templated
// Inputs
.index (index1[7:0])); // Templated
t_case_huge_sub s2 ( /*AUTOINST*/
// Outputs
.outa (outa2[9:0]), // Templated
.outb (outb2[1:0]), // Templated
.outc (outc2), // Templated
// Inputs
.index (index2[7:0])); // Templated
t_case_huge_sub s3 ( /*AUTOINST*/
// Outputs
.outa (outa3[9:0]), // Templated
.outb (outb3[1:0]), // Templated
.outc (outc3), // Templated
// Inputs
.index (index3[7:0])); // Templated
t_case_huge_sub s4 ( /*AUTOINST*/
// Outputs
.outa (outa4[9:0]), // Templated
.outb (outb4[1:0]), // Templated
.outc (outc4), // Templated
// Inputs
.index (index4[7:0])); // Templated
t_case_huge_sub s5 ( /*AUTOINST*/
// Outputs
.outa (outa5[9:0]), // Templated
.outb (outb5[1:0]), // Templated
.outc (outc5), // Templated
// Inputs
.index (index5[7:0])); // Templated
t_case_huge_sub s6 ( /*AUTOINST*/
// Outputs
.outa (outa6[9:0]), // Templated
.outb (outb6[1:0]), // Templated
.outc (outc6), // Templated
// Inputs
.index (index6[7:0])); // Templated
t_case_huge_sub s7 ( /*AUTOINST*/
// Outputs
.outa (outa7[9:0]), // Templated
.outb (outb7[1:0]), // Templated
.outc (outc7), // Templated
// Inputs
.index (index7[7:0])); // Templated
t_case_huge_sub4 q (/*AUTOINST*/
// Outputs
.outq (outq[9:0]),
// Inputs
.index (index[7:0]));
t_case_huge_sub4 q ( /*AUTOINST*/
// Outputs
.outq (outq[9:0]),
// Inputs
.index (index[7:0]));
integer cyc; initial cyc=1;
initial index = 10'h0;
integer cyc;
initial cyc = 1;
initial index = 10'h0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%x: %x\n",cyc,outr);
//$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1);
if (cyc==1) begin
index <= 10'h236;
end
if (cyc==2) begin
index <= 10'h022;
if (outsmall != 10'h282) $stop;
if (outr != 4'b0) $stop;
if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop;
if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop;
if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop;
if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop;
if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop;
if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==3) begin
index <= 10'h165;
if (outsmall != 10'h191) $stop;
if (outr != 4'h5) $stop;
if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop;
if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop;
if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop;
if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop;
if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==4) begin
index <= 10'h201;
if (outsmall != 10'h268) $stop;
if (outr != 4'h2) $stop;
if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop;
if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop;
if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop;
if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop;
if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==5) begin
index <= 10'h3ff;
if (outr != 4'hd) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==6) begin
index <= 10'h0;
if (outr != 4'hd) $stop;
if (outq != 10'h114) $stop;
end
if (cyc==7) begin
if (outr != 4'h4) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
//$write("%x: %x\n",cyc,outr);
//$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1);
if (cyc == 1) begin
index <= 10'h236;
end
end
if (cyc == 2) begin
index <= 10'h022;
if (outsmall != 10'h282) $stop;
if (outr != 4'b0) $stop;
if ({outa0, outb0, outc0} != {10'h282, 2'd3, 1'b0}) $stop;
if ({outa1, outb1, outc1} != {10'h21c, 2'd3, 1'b1}) $stop;
if ({outa2, outb2, outc2} != {10'h148, 2'd0, 1'b1}) $stop;
if ({outa3, outb3, outc3} != {10'h3c0, 2'd2, 1'b0}) $stop;
if ({outa4, outb4, outc4} != {10'h176, 2'd1, 1'b1}) $stop;
if ({outa5, outb5, outc5} != {10'h3fc, 2'd2, 1'b1}) $stop;
if ({outa6, outb6, outc6} != {10'h295, 2'd3, 1'b1}) $stop;
if ({outa7, outb7, outc7} != {10'h113, 2'd2, 1'b1}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc == 3) begin
index <= 10'h165;
if (outsmall != 10'h191) $stop;
if (outr != 4'h5) $stop;
if ({outa1, outb1, outc1} != {10'h379, 2'd1, 1'b0}) $stop;
if ({outa2, outb2, outc2} != {10'h073, 2'd0, 1'b0}) $stop;
if ({outa3, outb3, outc3} != {10'h2fd, 2'd3, 1'b1}) $stop;
if ({outa4, outb4, outc4} != {10'h2e0, 2'd3, 1'b1}) $stop;
if ({outa5, outb5, outc5} != {10'h337, 2'd1, 1'b1}) $stop;
if ({outa6, outb6, outc6} != {10'h2c7, 2'd3, 1'b1}) $stop;
if ({outa7, outb7, outc7} != {10'h19e, 2'd3, 1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc == 4) begin
index <= 10'h201;
if (outsmall != 10'h268) $stop;
if (outr != 4'h2) $stop;
if ({outa1, outb1, outc1} != {10'h111, 2'd1, 1'b0}) $stop;
if ({outa2, outb2, outc2} != {10'h1f9, 2'd0, 1'b0}) $stop;
if ({outa3, outb3, outc3} != {10'h232, 2'd0, 1'b1}) $stop;
if ({outa4, outb4, outc4} != {10'h255, 2'd3, 1'b0}) $stop;
if ({outa5, outb5, outc5} != {10'h34c, 2'd1, 1'b1}) $stop;
if ({outa6, outb6, outc6} != {10'h049, 2'd1, 1'b1}) $stop;
if ({outa7, outb7, outc7} != {10'h197, 2'd3, 1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc == 5) begin
index <= 10'h3ff;
if (outr != 4'hd) $stop;
if (outq != 10'h001) $stop;
end
if (cyc == 6) begin
index <= 10'h0;
if (outr != 4'hd) $stop;
if (outq != 10'h114) $stop;
end
if (cyc == 7) begin
if (outr != 4'h4) $stop;
end
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

14
test_regress/t/t_case_huge_sub.v
View File

@ -4,12 +4,14 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t_case_huge_sub (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
index
);
module t_case_huge_sub ( /*AUTOARG*/
// Outputs
outa,
outb,
outc,
// Inputs
index
);
input [7:0] index;
output logic [9:0] outa;

103
test_regress/t/t_case_inside.v
View File

@ -4,64 +4,71 @@
// SPDX-FileCopyrightText: 2014 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc;
initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
reg out1;
reg [4:0] out2;
sub sub (
.in(crc[23:0]),
.out1(out1),
.out2(out2)
);
always @ (posedge clk) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2);
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0],
out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {58'h0, out1, out2};
if (cyc == 0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
module sub ( /*AUTOARG*/
// Outputs
out1,
out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
case (in[3:0]) inside
default {out1,out2} = {1'b0,5'h0F}; // Note not last item, no : to cover parser
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
4'h4: {out1,out2} = {1'b1,5'h04};
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
endcase
end
always @* begin
case (in[3:0]) inside
default {out1, out2} = {1'b0, 5'h0F}; // Note not last item, no : to cover parser
4'h1, 4'h2, 4'h3: {out1, out2} = {1'b1, 5'h01};
4'h4: {out1, out2} = {1'b1, 5'h04};
[4'h6 : 4'h5]: {out1, out2} = {1'b1, 5'h05}; // order backwards, will not match
4'b100?: /*8,9*/{out1, out2} = {1'b1, 5'h08};
[4'hc : 4'hf]: {out1, out2} = {1'b1, 5'h0C};
endcase
end
endmodule

6
test_regress/t/t_case_inside_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_case_inside_bad.v:9:20: Illegal to have inside on a casex/casez
9 | casex (1'bx) inside
| ^~~~~~
%Error: t/t_case_inside_bad.v:9:18: Illegal to have inside on a casex/casez
9 | casex (1'bx) inside
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

10
test_regress/t/t_case_inside_bad.v
View File

@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
casex (1'bx) inside
default: $stop;
endcase
end
initial begin
casex (1'bx) inside
default: $stop;
endcase
end
endmodule

190
test_regress/t/t_case_itemwidth.v
View File

@ -4,117 +4,117 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
// Some inputs we'll set to random values
reg [6:0] addr;
reg [6:0] e0;
reg [5:0] e1;
reg [5:0] e2;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
wire [7:0] data;
reg [2:0] wrapcheck_a;
reg [2:0] wrapcheck_b;
test test ( /*AUTOINST*/
// Outputs
.data(data[7:0]),
// Inputs
.addr(addr[6:0]),
.e0(e0[6:0]),
.e1(e1[5:0]),
.e2(e2[5:0])
);
test test (/*AUTOINST*/
// Outputs
.data (data[7:0]),
// Inputs
.addr (addr[6:0]),
.e0 (e0[6:0]),
.e1 (e1[5:0]),
.e2 (e2[5:0]));
always @( /*AS*/ addr) begin
case (addr[2:0])
3'd0 + 3'd0: wrapcheck_a = 3'h0;
3'd0 + 3'd1: wrapcheck_a = 3'h1;
3'd0 + 3'd2: wrapcheck_a = 3'h2;
3'd0 + 3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
always @(/*AS*/addr) begin
case(addr[2:0])
3'd0+3'd0: wrapcheck_a = 3'h0;
3'd0+3'd1: wrapcheck_a = 3'h1;
3'd0+3'd2: wrapcheck_a = 3'h2;
3'd0+3'd3: wrapcheck_a = 3'h3;
default: wrapcheck_a = 3'h4;
endcase
case (addr[2:0])
3'd0 + 0: wrapcheck_b = 3'h0;
3'd1 + 1: wrapcheck_b = 3'h1;
3'd2 + 2: wrapcheck_b = 3'h2;
3'd3 + 3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
case(addr[2:0])
3'd0+0: wrapcheck_b = 3'h0;
3'd1+1: wrapcheck_b = 3'h1;
3'd2+2: wrapcheck_b = 3'h2;
3'd3+3: wrapcheck_b = 3'h3;
default: wrapcheck_b = 3'h4;
endcase
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
if (cyc==2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc==3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc==4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc==5) begin
if (data != 8'h00) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
integer cyc;
initial cyc = 1;
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc == 1) begin
addr <= 7'h28;
e0 <= 7'h11;
e1 <= 6'h02;
e2 <= 6'h03;
end
end
if (cyc == 2) begin
addr <= 7'h2b;
if (data != 8'h11) $stop;
end
if (cyc == 3) begin
addr <= 7'h2c;
if (data != 8'h03) $stop;
if (wrapcheck_a != 3'h3) $stop;
if (wrapcheck_b != 3'h4) $stop;
end
if (cyc == 4) begin
addr <= 7'h0;
if (data != 8'h00) $stop;
if (wrapcheck_a != 3'h4) $stop;
if (wrapcheck_b != 3'h2) $stop;
end
if (cyc == 5) begin
if (data != 8'h00) $stop;
end
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
/* verilator lint_off WIDTH */
`define AI 7'h28
`define AI 7'h28
module test (/*AUTOARG*/
// Outputs
data,
// Inputs
addr, e0, e1, e2
);
module test ( /*AUTOARG*/
// Outputs
data,
// Inputs
addr,
e0,
e1,
e2
);
output [7:0] data;
output [7:0] data;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
input [6:0] addr;
input [6:0] e0;
input [5:0] e1, e2;
reg [7:0] data;
reg [7:0] data;
always @(/*AS*/addr or e0 or e1 or e2)
begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI+1: data = e1;
`AI+2,
`AI+3: data = e2;
default: data = 0;
endcase
end
always @( /*AS*/ addr or e0 or e1 or e2) begin
case (addr)
`AI: data = {e0[6], 1'b0, e0[5:0]};
`AI + 1: data = e1;
`AI + 2, `AI + 3: data = e2;
default: data = 0;
endcase
end
endmodule

188
test_regress/t/t_case_nest.v
View File

@ -4,108 +4,114 @@
// SPDX-FileCopyrightText: 2006 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc;
initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
sub sub (
.in(crc[23:0]),
.out1(out1)
);
reg out1;
sub sub (.in(crc[23:0]), .out1(out1));
always @ (posedge clk) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1);
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {63'h0, out1};
if (cyc == 1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc == 90) begin
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
end
else if (cyc == 91) begin
end
else if (cyc == 92) begin
end
else if (cyc == 93) begin
end
else if (cyc == 94) begin
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1,
// Inputs
in
);
module sub ( /*AUTOARG*/
// Outputs
out1,
// Inputs
in
);
input [23:0] in;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
input [23:0] in;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;
always @* begin
casez (in[17:16])
2'b00: casez (in[2:0])
3'h0: out1[0] = in[0]^RANDOM[0];
3'h1: out1[0] = in[0]^RANDOM[1];
3'h2: out1[0] = in[0]^RANDOM[2];
3'h3: out1[0] = in[0]^RANDOM[3];
3'h4: out1[0] = in[0]^RANDOM[4];
3'h5: out1[0] = in[0]^RANDOM[5];
3'h6: out1[0] = in[0]^RANDOM[6];
3'h7: out1[0] = in[0]^RANDOM[7];
endcase
2'b01: casez (in[2:0])
3'h0: out1[0] = RANDOM[10];
3'h1: out1[0] = RANDOM[11];
3'h2: out1[0] = RANDOM[12];
3'h3: out1[0] = RANDOM[13];
3'h4: out1[0] = RANDOM[14];
3'h5: out1[0] = RANDOM[15];
3'h6: out1[0] = RANDOM[16];
3'h7: out1[0] = RANDOM[17];
endcase
2'b1?: casez (in[4])
1'b1: casez (in[2:0])
3'h0: out1[0] = RANDOM[20];
3'h1: out1[0] = RANDOM[21];
3'h2: out1[0] = RANDOM[22];
3'h3: out1[0] = RANDOM[23];
3'h4: out1[0] = RANDOM[24];
3'h5: out1[0] = RANDOM[25];
3'h6: out1[0] = RANDOM[26];
3'h7: out1[0] = RANDOM[27];
endcase
1'b0: casez (in[2:0])
3'h0: out1[0] = RANDOM[30];
3'h1: out1[0] = RANDOM[31];
3'h2: out1[0] = RANDOM[32];
3'h3: out1[0] = RANDOM[33];
3'h4: out1[0] = RANDOM[34];
3'h5: out1[0] = RANDOM[35];
3'h6: out1[0] = RANDOM[36];
3'h7: out1[0] = RANDOM[37];
endcase
endcase
always @* begin
casez (in[17:16])
2'b00:
casez (in[2:0])
3'h0: out1[0] = in[0] ^ RANDOM[0];
3'h1: out1[0] = in[0] ^ RANDOM[1];
3'h2: out1[0] = in[0] ^ RANDOM[2];
3'h3: out1[0] = in[0] ^ RANDOM[3];
3'h4: out1[0] = in[0] ^ RANDOM[4];
3'h5: out1[0] = in[0] ^ RANDOM[5];
3'h6: out1[0] = in[0] ^ RANDOM[6];
3'h7: out1[0] = in[0] ^ RANDOM[7];
endcase
end
2'b01:
casez (in[2:0])
3'h0: out1[0] = RANDOM[10];
3'h1: out1[0] = RANDOM[11];
3'h2: out1[0] = RANDOM[12];
3'h3: out1[0] = RANDOM[13];
3'h4: out1[0] = RANDOM[14];
3'h5: out1[0] = RANDOM[15];
3'h6: out1[0] = RANDOM[16];
3'h7: out1[0] = RANDOM[17];
endcase
2'b1?:
casez (in[4])
1'b1:
casez (in[2:0])
3'h0: out1[0] = RANDOM[20];
3'h1: out1[0] = RANDOM[21];
3'h2: out1[0] = RANDOM[22];
3'h3: out1[0] = RANDOM[23];
3'h4: out1[0] = RANDOM[24];
3'h5: out1[0] = RANDOM[25];
3'h6: out1[0] = RANDOM[26];
3'h7: out1[0] = RANDOM[27];
endcase
1'b0:
casez (in[2:0])
3'h0: out1[0] = RANDOM[30];
3'h1: out1[0] = RANDOM[31];
3'h2: out1[0] = RANDOM[32];
3'h3: out1[0] = RANDOM[33];
3'h4: out1[0] = RANDOM[34];
3'h5: out1[0] = RANDOM[35];
3'h6: out1[0] = RANDOM[36];
3'h7: out1[0] = RANDOM[37];
endcase
endcase
endcase
end
endmodule

146
test_regress/t/t_case_onehot.v
View File

@ -4,93 +4,91 @@
// SPDX-FileCopyrightText: 2009 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0] == 0 ? 3'd0 : crc[1:0] == 0 ? 3'd1 : crc[1:0] == 0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
Test test ( /*AUTOINST*/
// Outputs
.out(out[31:0]),
// Inputs
.clk(clk),
.in(in[2:0])
);
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
module Test ( /*AUTOARG*/
// Outputs
out,
// Inputs
clk,
in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule

340
test_regress/t/t_case_orig.v
View File

@ -4,184 +4,188 @@
// SPDX-FileCopyrightText: 2003 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg _ranit;
reg _ranit;
reg rnd;
reg [2:0] a;
reg [2:0] b;
reg [31:0] wide;
reg rnd;
reg [2:0] a;
reg [2:0] b;
reg [31:0] wide;
// surefire lint_off STMINI
initial _ranit = 0;
// surefire lint_off STMINI
initial _ranit = 0;
wire sigone1 = 1'b1;
wire sigone2 = 1'b1;
reg ok;
wire sigone1 = 1'b1;
wire sigone2 = 1'b1;
reg ok;
parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b??
parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b??
// Large case statements should be well optimizable.
reg [2:0] anot;
always @ (/*AS*/a) begin
casez (a)
default: anot = 3'b001;
3'd0: anot = 3'b111;
3'd1: anot = 3'b110;
3'd2: anot = 3'b101;
3'd3: anot = 3'b101;
3'd4: anot = 3'b011;
3'd5: anot = 3'b010;
3'd6: anot = 3'b001; // Same so folds with 7
endcase
end
// Large case statements should be well optimizable.
reg [2:0] anot;
always @( /*AS*/ a) begin
casez (a)
default: anot = 3'b001;
3'd0: anot = 3'b111;
3'd1: anot = 3'b110;
3'd2: anot = 3'b101;
3'd3: anot = 3'b101;
3'd4: anot = 3'b011;
3'd5: anot = 3'b010;
3'd6: anot = 3'b001; // Same so folds with 7
endcase
end
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
rnd <= 1;
$write("[%0t] t_case: Running\n", $time);
//
a = 3'b101;
b = 3'b111;
// verilator lint_off CASEX
casex (a)
default: $stop;
3'bx1x: $stop;
3'b100: $stop;
3'bx01: ;
endcase
casez (a)
default: $stop;
3'b?1?: $stop;
3'b100: $stop;
3'b?01: ;
endcase
casez (a)
default: $stop;
{1'b0, TWOUNKN}: $stop;
{1'b1, TWOUNKN}: ;
endcase
casez (b)
default: $stop;
{1'b0, TWOUNKN}: $stop;
{1'b1, TWOUNKN}: ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase
case(a[0])
default: ;
endcase
casex(a)
default: ;
3'b?0?: ;
endcase
// verilator lint_off CASEX
//This is illegal, the default occurs before the statements.
//case(a[0])
// default: $stop;
// 1'b1: ;
//endcase
//
wide = 32'h12345678;
casez (wide)
default: $stop;
32'h12345677,
32'h12345678,
32'h12345679: ;
endcase
//
ok = 0;
casez ({sigone1,sigone2})
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
2'b10, 2'b01: ;
2'b00: ;
default: ok=1'b1;
endcase
if (ok !== 1'b1) $stop;
//
if (rnd) begin
$write("");
end
//
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check parameters in case statements
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
parameter DSP_REGISTER_V = 6'h03;
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
reg [15:10] f_tmp_2s; // Delayed copy of F
reg p00_2s;
initial begin
alu_ctl_2s = 3'h1;
reg_addr_2s = 6'h3;
ir_slave_2s= 0;
f_tmp_2s= 0;
casex ({alu_ctl_2s,reg_addr_2s,
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
f_tmp_2s[11:10]})
default: p00_2s = 1'b0;
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
endcase
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
always @(posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
rnd <= 1;
$write("[%0t] t_case: Running\n", $time);
//
case ({1'b1, 1'b1})
a = 3'b101;
b = 3'b111;
// verilator lint_off CASEX
casex (a)
default: $stop;
{1'b1, p00_2s}: ;
3'bx1x: $stop;
3'b100: $stop;
3'bx01: ;
endcase
end
casez (a)
default: $stop;
3'b?1?: $stop;
3'b100: $stop;
3'b?01: ;
endcase
casez (a)
default: $stop;
{1'b0, TWOUNKN} : $stop;
{1'b1, TWOUNKN} : ;
endcase
casez (b)
default: $stop;
{1'b0, TWOUNKN} : $stop;
{1'b1, TWOUNKN} : ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase
case (a[0])
default: ;
endcase
casex (a)
default: ;
3'b?0?: ;
endcase
// verilator lint_off CASEX
//This is illegal, the default occurs before the statements.
//case(a[0])
// default: $stop;
// 1'b1: ;
//endcase
//
wide = 32'h12345678;
casez (wide)
default: $stop;
32'h12345677, 32'h12345678, 32'h12345679: ;
endcase
//
ok = 0;
casez ({
sigone1, sigone2
})
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
2'b10, 2'b01: ;
2'b00: ;
default: ok = 1'b1;
endcase
if (ok !== 1'b1) $stop;
//
// Check wide overlapping cases
// surefire lint_off CSEOVR
parameter ANY_STATE = 7'h??;
reg [19:0] foo;
initial begin
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
casez (foo)
default: $stop;
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
endcase
end
initial begin
foo = 20'b1010;
casex (foo[3:0])
default: $stop;
4'b0xxx,
4'b100x,
4'b11xx: $stop;
4'b1010: ;
endcase
end
initial begin
foo = 20'b1010;
ok = 1'b0;
// Test of RANGE(CONCAT reductions...
casex ({foo[3:2],foo[1:0],foo[3]})
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
5'bxx00x: $stop;
5'bxx01x: $stop;
5'bxx11x: $stop;
endcase
if (!ok) $stop;
end
if (rnd) begin
$write("");
end
//
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check parameters in case statements
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
parameter DSP_REGISTER_V = 6'h03;
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
reg [15:10] f_tmp_2s; // Delayed copy of F
reg p00_2s;
initial begin
alu_ctl_2s = 3'h1;
reg_addr_2s = 6'h3;
ir_slave_2s = 0;
f_tmp_2s = 0;
casex ({
alu_ctl_2s, reg_addr_2s, ir_slave_2s[7], ir_slave_2s[5:4], ir_slave_2s[1:0], f_tmp_2s[11:10]
})
default: p00_2s = 1'b0;
{ALU_DO_REGISTER, DSP_REGISTER_V, 1'bx, 2'bx, 2'bx, 2'bx} : p00_2s = 1'b1;
endcase
if (1'b0) $display("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
//
case ({
1'b1, 1'b1
})
default: $stop;
{1'b1, p00_2s} : ;
endcase
end
// Check wide overlapping cases
// surefire lint_off CSEOVR
parameter ANY_STATE = 7'h??;
reg [19:0] foo;
initial begin
foo = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 7'h04, 8'b0};
casez (foo)
default: $stop;
{1'b1, 1'b?, 1'b?, 1'b?, 1'b?, ANY_STATE, 8'b?} : $stop;
{1'b?, 1'b1, 1'b?, 1'b?, 1'b?, 7'h00, 8'b?} : $stop;
{1'b?, 1'b?, 1'b1, 1'b?, 1'b?, 7'h00, 8'b?} : $stop;
{1'b?, 1'b?, 1'b?, 1'b1, 1'b?, 7'h00, 8'b?} : $stop;
{1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h04, 8'b?} : ;
{1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h06, 8'hdf} : $stop;
{1'b?, 1'b?, 1'b?, 1'b?, 1'b?, 7'h06, 8'h00} : $stop;
endcase
end
initial begin
foo = 20'b1010;
casex (foo[3:0])
default: $stop;
4'b0xxx, 4'b100x, 4'b11xx: $stop;
4'b1010: ;
endcase
end
initial begin
foo = 20'b1010;
ok = 1'b0;
// Test of RANGE(CONCAT reductions...
casex ({
foo[3:2], foo[1:0], foo[3]
})
5'bxx10x: begin
ok = 1'b0;
foo = 20'd1;
ok = 1'b1;
end // Check multiple expressions
5'bxx00x: $stop;
5'bxx01x: $stop;
5'bxx11x: $stop;
endcase
if (!ok) $stop;
end
endmodule

48
test_regress/t/t_case_overlap_bad.out
View File

@ -1,27 +1,27 @@
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:13: Case conditions overlap
25 | 3'b001, 3'b000: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:24:13: ... Location of overlapping condition
24 | 3'b00?: $stop;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:7: Case conditions overlap
25 | 3'b001, 3'b000: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:24:7: ... Location of overlapping condition
24 | 3'b00?: $stop;
| ^~~~~~
... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest
... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message.
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:13: Case conditions overlap (example pattern 0x7)
30 | 3'b11?: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:29:13: ... Location of overlapping condition
29 | 3'b111, 3'b0??: v++;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:35:13: Case conditions overlap
35 | 3'b001: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:34:21: ... Location of overlapping condition
34 | 3'b000, 3'b001, 3'b010, 3'b011: v++;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:40:13: Case conditions overlap
40 | 3'b011: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:39:37: ... Location of overlapping condition
39 | 3'b000, 3'b001, 3'b010, 3'b011: v++;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:7: Case conditions overlap (example pattern 0x7)
30 | 3'b11?: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:29:7: ... Location of overlapping condition
29 | 3'b111, 3'b0??: v++;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:35:7: Case conditions overlap
35 | 3'b001: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:34:15: ... Location of overlapping condition
34 | 3'b000, 3'b001, 3'b010, 3'b011: v++;
| ^~~~~~
%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:40:7: Case conditions overlap
40 | 3'b011: $stop;
| ^~~~~~
t/t_case_overlap_bad.v:39:31: ... Location of overlapping condition
39 | 3'b000, 3'b001, 3'b010, 3'b011: v++;
| ^~~~~~
%Error: Exiting due to

60
test_regress/t/t_case_overlap_bad.v
View File

@ -5,40 +5,40 @@
// SPDX-License-Identifier: CC0-1.0
module t;
t1 i_t1();
t1 i_t1 ();
endmodule
module t1;
int v = 0;
int v = 0;
logic [2:0] state;
logic [2:0] state;
initial begin
state = 2;
casez (state)
3'b11?, 3'b???: v++;
default;
endcase
casez (state)
3'b00?: $stop;
3'b001, 3'b000: $stop;
default;
endcase
casez (state)
3'b111, 3'b0??: v++;
3'b11?: $stop;
default;
endcase
casez (state)
3'b000, 3'b001, 3'b010, 3'b011: v++;
3'b001: $stop;
default;
endcase
casez (state)
3'b000, 3'b001, 3'b010, 3'b011: v++;
3'b011: $stop;
default;
endcase
end
initial begin
state = 2;
casez (state)
3'b11?, 3'b???: v++;
default;
endcase
casez (state)
3'b00?: $stop;
3'b001, 3'b000: $stop;
default;
endcase
casez (state)
3'b111, 3'b0??: v++;
3'b11?: $stop;
default;
endcase
casez (state)
3'b000, 3'b001, 3'b010, 3'b011: v++;
3'b001: $stop;
default;
endcase
casez (state)
3'b000, 3'b001, 3'b010, 3'b011: v++;
3'b011: $stop;
default;
endcase
end
endmodule

165
test_regress/t/t_case_reducer.v
View File

@ -4,100 +4,98 @@
// SPDX-FileCopyrightText: 2012 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[6:0]),
// Inputs
.clk (clk),
.operand_a (operand_a[7:0]),
.operand_b (operand_b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a
(
Test test ( /*AUTOINST*/
// Outputs
.out(out[6:0]),
// Inputs
.data_i (operand_a),
.out (clz_a));
.clk(clk),
.operand_a(operand_a[7:0]),
.operand_b(operand_b[7:0])
);
clz u_clz_b
(
// Inputs
.data_i (operand_b),
.out (clz_b));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
assign out = clz_a - clz_b;
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
always @(posedge clk)
$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a (
// Inputs
.data_i(operand_a),
.out(clz_a)
);
clz u_clz_b (
// Inputs
.data_i(operand_b),
.out(clz_b)
);
assign out = clz_a - clz_b;
`ifdef TEST_VERBOSE
always @(posedge clk) $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
`endif
endmodule
// verilog_format: off
`define def_0000_001x 8'b0000_0010, 8'b0000_0011
`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
@ -204,7 +202,6 @@ endmodule
`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
module clz(
input wire [7:0] data_i,
output wire [6:0] out
@ -276,4 +273,4 @@ module clz(
assign out = {4'b0000, clz_byte1};
endmodule // clz
endmodule

57
test_regress/t/t_case_string.v
View File

@ -4,36 +4,35 @@
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
string mystr;
reg [2:0] cyc; initial cyc = 0;
string mystr;
reg [2:0] cyc;
initial cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) if (mystr != "case-1") $stop;
if (cyc == 4) if (mystr != "case-4") $stop;
if (cyc == 6) if (mystr != "bad-default") $stop;
if (cyc == 7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) if (mystr != "case-1") $stop;
if (cyc == 4) if (mystr != "case-4") $stop;
if (cyc == 6) if (mystr != "bad-default") $stop;
if (cyc == 7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @ (cyc) begin
// verilator lint_off CASEINCOMPLETE
case (cyc)
3'b000: mystr = "case-0";
3'b001: mystr = "case-1";
3'b010: mystr = "case-2";
3'b100: mystr = "case-4";
3'b101: mystr = "case-5";
default: mystr = "bad-default";
endcase
//$display("with_case: %d = %s", cyc, mystr);
end
always @(cyc) begin
// verilator lint_off CASEINCOMPLETE
case (cyc)
3'b000: mystr = "case-0";
3'b001: mystr = "case-1";
3'b010: mystr = "case-2";
3'b100: mystr = "case-4";
3'b101: mystr = "case-5";
default: mystr = "bad-default";
endcase
//$display("with_case: %d = %s", cyc, mystr);
end
endmodule

20
test_regress/t/t_case_string2.v
View File

@ -6,16 +6,16 @@
module t;
function automatic string broken_case(input string some_string);
case(some_string)
"alpha": return "alpha";
default: return "beta";
function automatic string broken_case(input string some_string);
case (some_string)
"alpha": return "alpha";
default: return "beta";
endcase
endfunction
endfunction
initial begin
$display(broken_case("gamma"));
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$display(broken_case("gamma"));
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

157
test_regress/t/t_case_wild.v
View File

@ -4,90 +4,93 @@
// SPDX-FileCopyrightText: 2006 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc;
initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (
.in(crc[23:0]),
.out1(out1),
.out2(out2)
);
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63] ^ sum[2] ^ sum[0]} ^ {58'h0, out1, out2};
if (cyc == 0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc == 90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc == 91) begin
end
else if (cyc == 92) begin
end
else if (cyc == 93) begin
end
else if (cyc == 94) begin
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
module sub ( /*AUTOARG*/
// Outputs
out1,
out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
always @* begin
casez (in)
24'b0000_0000_0000_0000_0000_0000: {out1, out2} = {1'b0, 5'h00};
24'b????_????_????_????_????_???1: {out1, out2} = {1'b1, 5'h00};
24'b????_????_????_????_????_??10: {out1, out2} = {1'b1, 5'h01};
24'b????_????_????_????_????_?100: {out1, out2} = {1'b1, 5'h02};
24'b????_????_????_????_????_1000: {out1, out2} = {1'b1, 5'h03};
24'b????_????_????_????_???1_0000: {out1, out2} = {1'b1, 5'h04};
24'b????_????_????_????_??10_0000: {out1, out2} = {1'b1, 5'h05};
24'b????_????_????_????_?100_0000: {out1, out2} = {1'b1, 5'h06};
24'b????_????_????_????_1000_0000: {out1, out2} = {1'b1, 5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h17};
24'b?100_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h16};
24'b??10_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h15};
24'b???1_0000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h14};
24'b????_1000_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h13};
24'b????_?100_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h12};
24'b????_??10_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h11};
24'b????_???1_0000_0000_0000_0000: {out1, out2} = {1'b1, 5'h10};
24'b????_????_1000_0000_0000_0000: {out1, out2} = {1'b1, 5'h0f};
24'b????_????_?100_0000_0000_0000: {out1, out2} = {1'b1, 5'h0e};
24'b????_????_??10_0000_0000_0000: {out1, out2} = {1'b1, 5'h0d};
24'b????_????_???1_0000_0000_0000: {out1, out2} = {1'b1, 5'h0c};
24'b????_????_????_1000_0000_0000: {out1, out2} = {1'b1, 5'h0b};
24'b????_????_????_?100_0000_0000: {out1, out2} = {1'b1, 5'h0a};
24'b????_????_????_??10_0000_0000: {out1, out2} = {1'b1, 5'h09};
24'b????_????_????_???1_0000_0000: {out1, out2} = {1'b1, 5'h08};
endcase
end
endmodule

60
test_regress/t/t_case_write1.v
View File

@ -6,41 +6,39 @@
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write1_tasks tasks ();
t_case_write1_tasks tasks ();
integer cyc;
initial cyc = 0;
integer cyc; initial cyc = 0;
always @(posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc == 1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc == 90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

6997
test_regress/t/t_case_write1_tasks.v
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File diff suppressed because it is too large Load Diff

60
test_regress/t/t_case_write2.v
View File

@ -6,41 +6,39 @@
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write2_tasks tasks ();
t_case_write2_tasks tasks ();
integer cyc;
initial cyc = 0;
integer cyc; initial cyc = 0;
always @(posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc == 1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc == 90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

7431
test_regress/t/t_case_write2_tasks.v
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File diff suppressed because it is too large Load Diff

106
test_regress/t/t_case_x.v
View File

@ -6,61 +6,61 @@
module t;
reg [3:0] value;
reg [3:0] valuex;
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_case_x_bad.out
View File

@ -1,11 +1,11 @@
%Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's)
14 | casex (value)
| ^~~~~
%Warning-CASEX: t/t_case_x_bad.v:14:5: Suggest casez (with ?'s) in place of casex (with X's)
14 | casex (value)
| ^~~~~
... For warning description see https://verilator.org/warn/CASEX?v=latest
... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message.
%Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez)
19 | 4'b1xxx: $stop;
| ^~~~~~~
%Warning-CASEWITHX: t/t_case_x_bad.v:19:7: Use of x/? constant in case statement, (perhaps intended casex/casez)
19 | 4'b1xxx: $stop;
| ^~~~~~~
... For warning description see https://verilator.org/warn/CASEWITHX?v=latest
... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message.
%Error: Exiting due to

30
test_regress/t/t_case_x_bad.v
View File

@ -4,21 +4,21 @@
// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
value
);
module t ( /*AUTOARG*/
// Inputs
value
);
input [3:0] value;
always @ (/*AS*/value) begin
casex (value)
default: $stop;
endcase
case (value)
4'b0000: $stop;
4'b1xxx: $stop;
default: $stop;
endcase
end
input [3:0] value;
always @( /*AS*/ value) begin
casex (value)
default: $stop;
endcase
case (value)
4'b0000: $stop;
4'b1xxx: $stop;
default: $stop;
endcase
end
endmodule

6
test_regress/t/t_case_zx_bad.out
View File

@ -1,6 +1,6 @@
%Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant)
16 | 4'b1xxx: $stop;
| ^~~~~~~
%Warning-CASEWITHX: t/t_case_zx_bad.v:16:7: Use of x constant in casez statement, (perhaps intended ?/z in constant)
16 | 4'b1xxx: $stop;
| ^~~~~~~
... For warning description see https://verilator.org/warn/CASEWITHX?v=latest
... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message.
%Error: Exiting due to

24
test_regress/t/t_case_zx_bad.v
View File

@ -4,18 +4,18 @@
// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
value
);
module t ( /*AUTOARG*/
// Inputs
value
);
input [3:0] value;
always @ (/*AS*/value) begin
casez (value)
4'b0000: $stop;
4'b1xxx: $stop;
default: $stop;
endcase
end
input [3:0] value;
always @( /*AS*/ value) begin
casez (value)
4'b0000: $stop;
4'b1xxx: $stop;
default: $stop;
endcase
end
endmodule

38
test_regress/t/t_cast_class.v
View File

@ -5,35 +5,35 @@
// SPDX-License-Identifier: CC0-1.0
class Base;
int b;
int b;
endclass
class BaseExtended extends Base;
int e;
int e;
endclass
module t;
Base v_cls_a;
BaseExtended v_cls_ab;
BaseExtended v_cls_ab1;
Base v_cls_a;
BaseExtended v_cls_ab;
BaseExtended v_cls_ab1;
initial begin
v_cls_a = Base'(null);
if (v_cls_a != null) $stop;
initial begin
v_cls_a = Base'(null);
if (v_cls_a != null) $stop;
v_cls_ab = new;
v_cls_ab.b = 10;
v_cls_ab.e = 20;
v_cls_ab = new;
v_cls_ab.b = 10;
v_cls_ab.e = 20;
v_cls_ab1 = BaseExtended'(v_cls_ab);
if (v_cls_ab1.b != 10) $stop;
if (v_cls_ab1.e != 20) $stop;
v_cls_ab1 = BaseExtended'(v_cls_ab);
if (v_cls_ab1.b != 10) $stop;
if (v_cls_ab1.e != 20) $stop;
v_cls_a = Base'(v_cls_ab);
if (v_cls_a.b != 10) $stop;
v_cls_a = Base'(v_cls_ab);
if (v_cls_a.b != 10) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_cast_class_incompat_bad.out
View File

@ -1,11 +1,11 @@
%Error: t/t_cast_class_incompat_bad.v:26:28: Dynamic, not static cast, required to cast 'class{}BaseExtended' from 'class{}Base'
%Error: t/t_cast_class_incompat_bad.v:26:26: Dynamic, not static cast, required to cast 'class{}BaseExtended' from 'class{}Base'
: ... note: In instance 't'
: ... Suggest dynamic $cast
26 | cls_ab = BaseExtended'(cls_a);
| ^
26 | cls_ab = BaseExtended'(cls_a);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_cast_class_incompat_bad.v:27:20: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended'
%Error: t/t_cast_class_incompat_bad.v:27:18: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended'
: ... note: In instance 't'
27 | other = Other'(cls_ab);
| ^
27 | other = Other'(cls_ab);
| ^
%Error: Exiting due to

16
test_regress/t/t_cast_class_incompat_bad.v
View File

@ -17,14 +17,14 @@ typedef Other Other_t;
module t;
Base_t cls_a;
BaseExtended_t cls_ab;
Other_t other;
Base_t cls_a;
BaseExtended_t cls_ab;
Other_t other;
initial begin
cls_a = new;
cls_ab = BaseExtended'(cls_a); // bad-need dyn
other = Other'(cls_ab); // bad-incompat
end
initial begin
cls_a = new;
cls_ab = BaseExtended'(cls_a); // bad-need dyn
other = Other'(cls_ab); // bad-incompat
end
endmodule

16
test_regress/t/t_cast_param_logic.v
View File

@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2022 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t
#(
module t #(
parameter type data_t = logic
)
(
input data_t[7:0] in_data
);
) (
input data_t [7:0] in_data
);
typedef data_t[7:0] in_data_t;
typedef data_t [7:0] in_data_t;
in_data_t out_data;
always_comb out_data = in_data_t'(in_data);
in_data_t out_data;
always_comb out_data = in_data_t'(in_data);
endmodule

40
test_regress/t/t_cast_param_type.v
View File

@ -4,33 +4,37 @@
// SPDX-FileCopyrightText: 2022 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
typedef enum logic [1:0] {A, B, C } letters_t;
typedef enum logic [1:0] {
A,
B,
C
} letters_t;
module SubA
#(parameter letters_t LETTER = A)
();
module SubA #(
parameter letters_t LETTER = A
) ();
endmodule
module SubB
#(parameter letters_t LETTER = letters_t'(0))
();
module SubB #(
parameter letters_t LETTER = letters_t'(0)
) ();
endmodule
function automatic letters_t lfunc(int a);
return letters_t'(1);
return letters_t'(1);
endfunction
module t;
localparam FMT = lfunc(1);
localparam FMT = lfunc(1);
SubA suba0 ();
SubA #(.LETTER(letters_t'(1))) suba1 ();
SubB #(.LETTER(letters_t'(1))) subb2 ();
SubA suba0 ();
SubA #(.LETTER(letters_t'(1))) suba1 ();
SubB #(.LETTER(letters_t'(1))) subb2 ();
initial begin
if (lfunc(1) != B) $stop;
if (FMT != B) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
if (lfunc(1) != B) $stop;
if (FMT != B) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

22
test_regress/t/t_cast_signed.v
View File

@ -6,18 +6,18 @@
module t;
logic [7:0] smaller;
logic [15:0] bigger;
typedef logic [15:0] bigger_t;
logic [7:0] smaller;
logic [15:0] bigger;
typedef logic [15:0] bigger_t;
initial begin
smaller = 8'hfa;
bigger = bigger_t'(signed'(smaller));
$display("%x", bigger); // NOCOMMIT
if (bigger != 16'hfffa) $stop;
initial begin
smaller = 8'hfa;
bigger = bigger_t'(signed'(smaller));
$display("%x", bigger); // NOCOMMIT
if (bigger != 16'hfffa) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_cast_size_bad.out
View File

@ -1,12 +1,12 @@
%Error: t/t_cast_size_bad.v:14:15: Size-changing cast to zero or negative size
%Error: t/t_cast_size_bad.v:14:13: Size-changing cast to zero or negative size
: ... note: In instance 't'
14 | b = (-1)'(a);
| ^
14 | b = (-1)'(a);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
%Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:7: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
: ... note: In instance 't'
14 | b = (-1)'(a);
| ^
14 | b = (-1)'(a);
| ^
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
%Error: Exiting due to

12
test_regress/t/t_cast_size_bad.v
View File

@ -6,12 +6,12 @@
module t;
int a;
reg [3:0] b;
int a;
reg [3:0] b;
initial begin
a = 1;
b = (-1)'(a); // Bad
end
initial begin
a = 1;
b = (-1)'(a); // Bad
end
endmodule

30
test_regress/t/t_cast_stream.v
View File

@ -10,26 +10,26 @@
// verilog_format: on
typedef enum {
UVM_TLM_READ_COMMAND,
UVM_TLM_WRITE_COMMAND,
UVM_TLM_IGNORE_COMMAND
UVM_TLM_READ_COMMAND,
UVM_TLM_WRITE_COMMAND,
UVM_TLM_IGNORE_COMMAND
} uvm_tlm_command_e;
module t;
initial begin
automatic bit array[] = new [8];
automatic int unsigned m_length;
automatic uvm_tlm_command_e m_command;
initial begin
automatic bit array[] = new[8];
automatic int unsigned m_length;
automatic uvm_tlm_command_e m_command;
m_length = 2;
array = '{0, 0, 0, 0, 0, 0, 1, 0};
array = new [$bits(m_length)] (array);
m_command = uvm_tlm_command_e'({ << bit { array }});
m_length = 2;
array = '{0, 0, 0, 0, 0, 0, 1, 0};
array = new[$bits(m_length)] (array);
m_command = uvm_tlm_command_e'({<<bit{array}});
`checkh(m_command, 'h40)
$write("*-* All Finished *-*\n");
$finish;
end
`checkh(m_command, 'h40)
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

183
test_regress/t/t_cast_types.v
View File

@ -4,25 +4,25 @@
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
`define TRY_ASSIGN(a,b) a = b
`define TRY_CAST(a,b) a = type(a)'(b)
`define TRY_ASSIGN(a, b) a = b
`define TRY_CAST(a, b) a = type(a)'(b)
`ifdef VERILATOR
`define TRY_DYNAMIC(a,b) // UNSUP $cast
`define TRY_BAD(a,b) // UNSUP $cast
`define TRY_DYNAMIC(a, b) // UNSUP $cast
`define TRY_BAD(a, b) // UNSUP $cast
`else
`define TRY_DYNAMIC(a,b) if (1 != $cast(a, b)) $stop
`define TRY_BAD(a,b) if (0 != $cast(a, b)) $stop
`define TRY_DYNAMIC(a, b) if (1 != $cast(a, b)) $stop
`define TRY_BAD(a, b) if (0 != $cast(a, b)) $stop
`endif
`define MATCHING(a,b) `TRY_ASSIGN(a,b)
`define EQUIVALENT(a,b) `TRY_ASSIGN(a,b)
`define COMPATIBLE(a,b) `TRY_ASSIGN(a,b)
`define CAST_COMPATIBLE(a,b) `TRY_CAST(a,b)
`define CAST_COMPATIBLE_ENUM(a,b) `TRY_CAST(a,b)
`define CAST_COMPATIBLE_DYNAMIC(a,b) `TRY_DYNAMIC(a,b)
`define INCOMPATIBLE(a,b) `TRY_BAD(a,b)
`define MATCHING(a, b) `TRY_ASSIGN(a,b)
`define EQUIVALENT(a, b) `TRY_ASSIGN(a,b)
`define COMPATIBLE(a, b) `TRY_ASSIGN(a,b)
`define CAST_COMPATIBLE(a, b) `TRY_CAST(a,b)
`define CAST_COMPATIBLE_ENUM(a, b) `TRY_CAST(a,b)
`define CAST_COMPATIBLE_DYNAMIC(a, b) `TRY_DYNAMIC(a,b)
`define INCOMPATIBLE(a, b) `TRY_BAD(a,b)
`define STRING_LITERAL "literal" // IEEE 5.9 - to packed or unpacked per IEEE 6.24
`define STRING_LITERAL "literal" // IEEE 5.9 - to packed or unpacked per IEEE 6.24
class Base;
endclass
@ -31,106 +31,115 @@ endclass
class Other;
endclass
typedef enum { A_ZERO, A_ONE } Enum_A_t;
typedef enum { B_ZERO, B_ONE } Enum_B_t;
typedef enum {
A_ZERO,
A_ONE
} Enum_A_t;
typedef enum {
B_ZERO,
B_ONE
} Enum_B_t;
typedef int int_t;
typedef struct packed { int a; int b; } stpack_t;
typedef struct packed {
int a;
int b;
} stpack_t;
typedef bit signed [7:0] simple_a_t;
typedef bit signed [7:0] simple_a1_t;
module t;
real v_real; // IEEE 6.12.2 - by rounding
string v_string;
int v_int;
int_t v_int_t;
chandle v_chandle;
Enum_A_t v_enum_a;
Enum_A_t v_enum_a1;
Enum_B_t v_enum_b;
stpack_t v_stpack_a;
stpack_t v_stpack_a1;
simple_a_t v_simple_a;
simple_a1_t v_simple_a1;
int v_unpk_a[2][3];
int v_unpk_a1[2][3];
int v_assoc_a[string];
int v_assoc_a1[string];
int v_assoc_b[int];
int v_assoc_c[bit[31:0]];
real v_real; // IEEE 6.12.2 - by rounding
string v_string;
int v_int;
int_t v_int_t;
chandle v_chandle;
Enum_A_t v_enum_a;
Enum_A_t v_enum_a1;
Enum_B_t v_enum_b;
stpack_t v_stpack_a;
stpack_t v_stpack_a1;
simple_a_t v_simple_a;
simple_a1_t v_simple_a1;
int v_unpk_a[2][3];
int v_unpk_a1[2][3];
int v_assoc_a[string];
int v_assoc_a1[string];
int v_assoc_b[int];
int v_assoc_c[bit [31:0]];
int v_q_a[$];
int v_q_a1[$];
real v_q_b[$];
int v_q_a[$];
int v_q_a1[$];
real v_q_b[$];
bit [3:0][7:0] v_2thirtytwo_a;
bit [3:0][7:0] v_2thirtytwo_b;
logic [3:0][7:0] v_4thirtytwo_a;
logic [3:0][7:0] v_4thirtytwo_b;
bit [3:0][7:0] v_2thirtytwo_a;
bit [3:0][7:0] v_2thirtytwo_b;
logic [3:0][7:0] v_4thirtytwo_a;
logic [3:0][7:0] v_4thirtytwo_b;
Base v_cls_a;
Base v_cls_a1;
BaseExtended v_cls_ab;
Other v_cls_b;
Base v_cls_a;
Base v_cls_a1;
BaseExtended v_cls_ab;
Other v_cls_b;
// verilator lint_off REALCVT
// verilator lint_off REALCVT
initial begin
// 6.22.1
`MATCHING(v_real, v_real);
`MATCHING(v_string, v_string);
`MATCHING(v_int, v_int);
`MATCHING(v_chandle, v_chandle);
`MATCHING(v_int, v_int_t);
`MATCHING(v_stpack_a, v_stpack_a1);
`MATCHING(v_simple_a, v_simple_a1);
`MATCHING(v_unpk_a, v_unpk_a1);
`MATCHING(v_assoc_a, v_assoc_a1);
`MATCHING(v_q_a, v_q_a1);
`MATCHING(v_int, v_2thirtytwo_a);
`MATCHING(v_cls_a, v_cls_a1);
`MATCHING(v_cls_a, v_cls_ab);
// 6.22.2
`EQUIVALENT(v_int, v_2thirtytwo_a);
initial begin
// 6.22.1
`MATCHING(v_real, v_real);
`MATCHING(v_string, v_string);
`MATCHING(v_int, v_int);
`MATCHING(v_chandle, v_chandle);
`MATCHING(v_int, v_int_t);
`MATCHING(v_stpack_a, v_stpack_a1);
`MATCHING(v_simple_a, v_simple_a1);
`MATCHING(v_unpk_a, v_unpk_a1);
`MATCHING(v_assoc_a, v_assoc_a1);
`MATCHING(v_q_a, v_q_a1);
`MATCHING(v_int, v_2thirtytwo_a);
`MATCHING(v_cls_a, v_cls_a1);
`MATCHING(v_cls_a, v_cls_ab);
// 6.22.2
`EQUIVALENT(v_int, v_2thirtytwo_a);
`ifndef NC
`ifndef VCS
`EQUIVALENT(v_assoc_b, v_assoc_c); // Spec says equivalent, but simulators disagree
`EQUIVALENT(v_assoc_b, v_assoc_c); // Spec says equivalent, but simulators disagree
`endif
`endif
// 6.22.3
`COMPATIBLE(v_string, `STRING_LITERAL);
`COMPATIBLE(v_int, v_enum_a);
`COMPATIBLE(v_int, v_real);
`COMPATIBLE(v_real, v_int);
// 6.22.4->5.9
// 6.22.3
`COMPATIBLE(v_string, `STRING_LITERAL);
`COMPATIBLE(v_int, v_enum_a);
`COMPATIBLE(v_int, v_real);
`COMPATIBLE(v_real, v_int);
// 6.22.4->5.9
`ifndef NC
`CAST_COMPATIBLE(v_string, v_int);
`CAST_COMPATIBLE(v_string, v_int);
`endif
// 6.22.4->6.19.3
// 6.22.4->6.19.3
`ifndef NC
`CAST_COMPATIBLE_ENUM(v_enum_a, v_int);
`CAST_COMPATIBLE_ENUM(v_enum_a, v_enum_b);
`CAST_COMPATIBLE_ENUM(v_enum_a, v_int);
`CAST_COMPATIBLE_ENUM(v_enum_a, v_enum_b);
`endif
`CAST_COMPATIBLE_DYNAMIC(v_cls_ab, v_cls_a);
// 6.22.5 incompatible
`INCOMPATIBLE(v_cls_ab, v_int);
`CAST_COMPATIBLE_DYNAMIC(v_cls_ab, v_cls_a);
// 6.22.5 incompatible
`INCOMPATIBLE(v_cls_ab, v_int);
`ifndef VCS
`INCOMPATIBLE(v_real, v_assoc_a);
`INCOMPATIBLE(v_real, v_q_a);
`INCOMPATIBLE(v_real, v_assoc_a);
`INCOMPATIBLE(v_real, v_q_a);
`endif
`ifndef VCS
`ifndef VERILATOR
`INCOMPATIBLE(v_chandle, v_int);
`endif
`ifndef VERILATOR
`INCOMPATIBLE(v_chandle, v_int);
`endif
`endif
`ifndef NC
`INCOMPATIBLE(v_cls_a, v_cls_b);
`INCOMPATIBLE(v_cls_a, v_cls_b);
`endif
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

54
test_regress/t/t_class_assign_bad.out
View File

@ -1,38 +1,38 @@
%Error: t/t_class_assign_bad.v:28:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
%Error: t/t_class_assign_bad.v:30:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
: ... note: In instance 't'
28 | c = 0;
| ^
30 | c = 0;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_class_assign_bad.v:29:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
%Error: t/t_class_assign_bad.v:31:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
: ... note: In instance 't'
29 | c = 1;
| ^
%Error: t/t_class_assign_bad.v:30:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2'
31 | c = 1;
| ^
%Error: t/t_class_assign_bad.v:32:7: Assign RHS expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2'
: ... note: In instance 't'
30 | c = c2;
| ^
%Error: t/t_class_assign_bad.v:31:13: Assign RHS expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls'
32 | c = c2;
| ^
%Error: t/t_class_assign_bad.v:33:11: Assign RHS expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls'
: ... note: In instance 't'
31 | c_ext = c;
| ^
%Error: t/t_class_assign_bad.v:32:11: Assign RHS expects a CLASSREFDTYPE 'Cls2', got CLASSREFDTYPE 'Cls'
: ... note: In instance 't'
32 | ct2 = c;
33 | c_ext = c;
| ^
%Error: t/t_class_assign_bad.v:34:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
%Error: t/t_class_assign_bad.v:34:9: Assign RHS expects a CLASSREFDTYPE 'Cls2', got CLASSREFDTYPE 'Cls'
: ... note: In instance 't'
34 | t(0);
| ^
%Error: t/t_class_assign_bad.v:35:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
34 | ct2 = c;
| ^
%Error: t/t_class_assign_bad.v:36:5: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
: ... note: In instance 't'
35 | t(1);
| ^
%Error: t/t_class_assign_bad.v:36:7: Function Argument expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2'
36 | t(0);
| ^
%Error: t/t_class_assign_bad.v:37:5: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic'
: ... note: In instance 't'
36 | t(c2);
| ^
%Error: t/t_class_assign_bad.v:37:7: Function Argument expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls'
37 | t(1);
| ^
%Error: t/t_class_assign_bad.v:38:5: Function Argument expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2'
: ... note: In instance 't'
37 | f(c);
| ^
38 | t(c2);
| ^
%Error: t/t_class_assign_bad.v:39:5: Function Argument expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls'
: ... note: In instance 't'
39 | f(c);
| ^
%Error: Exiting due to

36
test_regress/t/t_class_assign_bad.v
View File

@ -16,24 +16,26 @@ endclass
typedef Cls2 cls2_t;
module t;
Cls c;
Cls2 c2;
cls2_t ct2;
ClsExt c_ext;
Cls c;
Cls2 c2;
cls2_t ct2;
ClsExt c_ext;
task t(Cls c); endtask
function void f(ClsExt c); endfunction
task t(Cls c);
endtask
function void f(ClsExt c);
endfunction
initial begin
c = 0;
c = 1;
c = c2;
c_ext = c;
ct2 = c;
initial begin
c = 0;
c = 1;
c = c2;
c_ext = c;
ct2 = c;
t(0);
t(1);
t(c2);
f(c);
end
t(0);
t(1);
t(c2);
f(c);
end
endmodule

120
test_regress/t/t_class_assign_cond.v
View File

@ -5,89 +5,89 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
int f;
function new(int x);
f = x;
endfunction
int f;
function new(int x);
f = x;
endfunction
endclass
class ExtendCls extends Cls;
function new(int x);
super.new(x);
endfunction
function new(int x);
super.new(x);
endfunction
endclass
class AnotherExtendCls extends Cls;
function new(int x);
super.new(x);
endfunction
function new(int x);
super.new(x);
endfunction
endclass
class ExtendExtendCls extends ExtendCls;
function new(int x);
super.new(x);
endfunction
function new(int x);
super.new(x);
endfunction
endclass
module t;
typedef ExtendCls ExtendCls_t;
typedef ExtendCls ExtendCls_t;
initial begin
automatic Cls cls1 = null;
automatic Cls cls2 = null;
automatic ExtendCls_t ext_cls = null;
automatic AnotherExtendCls an_ext_cls = null;
automatic ExtendExtendCls ext_ext_cls = null;
int r;
initial begin
automatic Cls cls1 = null;
automatic Cls cls2 = null;
automatic ExtendCls_t ext_cls = null;
automatic AnotherExtendCls an_ext_cls = null;
automatic ExtendExtendCls ext_ext_cls = null;
int r;
cls1 = (cls1 == null) ? cls2 : cls1;
if (cls1 != null) $stop;
cls1 = (cls1 == null) ? cls2 : cls1;
if (cls1 != null) $stop;
cls1 = new(1);
cls1 = (cls1 == null) ? cls2 : cls1;
if (cls1.f != 1) $stop;
cls1 = new(1);
cls1 = (cls1 == null) ? cls2 : cls1;
if (cls1.f != 1) $stop;
cls1 = (cls1 != null) ? cls2 : cls1;
if (cls1 != null) $stop;
cls1 = (cls1 != null) ? cls2 : cls1;
if (cls1 != null) $stop;
cls1 = new(1);
cls2 = new(2);
cls1 = (cls1 != null) ? cls2 : cls1;
if (cls1.f != 2) $stop;
cls1 = new(1);
cls2 = new(2);
cls1 = (cls1 != null) ? cls2 : cls1;
if (cls1.f != 2) $stop;
cls1 = null;
cls1 = (ext_cls != null) ? ext_cls : cls2;
if (cls1.f != 2) $stop;
cls1 = null;
cls1 = (ext_cls != null) ? ext_cls : cls2;
if (cls1.f != 2) $stop;
ext_cls = new(3);
cls1 = (ext_cls != null) ? ext_cls : cls2;
if (cls1.f != 3) $stop;
ext_cls = new(3);
cls1 = (ext_cls != null) ? ext_cls : cls2;
if (cls1.f != 3) $stop;
ext_ext_cls = new(4);
an_ext_cls = new(5);
cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls;
if (cls1.f != 5) $stop;
ext_ext_cls = new(4);
an_ext_cls = new(5);
cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls;
if (cls1.f != 5) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? ext_cls : null;
if (cls1 != null && cls1.f != 3) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? ext_cls : null;
if (cls1 != null && cls1.f != 3) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? null : ext_cls;
if (cls1 != null && cls1.f != 3) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? null : ext_cls;
if (cls1 != null && cls1.f != 3) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? null : null;
if (cls1 != null) $stop;
ext_cls = new(3);
r = $random;
cls1 = r[0] ? null : null;
if (cls1 != null) $stop;
ext_cls = new(3);
cls1 = (ext_cls == null) ? null : null;
if (cls1 != null) $stop;
ext_cls = new(3);
cls1 = (ext_cls == null) ? null : null;
if (cls1 != null) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

34
test_regress/t/t_class_assign_cond_bad.out
View File

@ -1,22 +1,22 @@
%Error: t/t_class_assign_cond_bad.v:22:25: Incompatible types of operands of condition operator: CLASSREFDTYPE 'Cls1' and CLASSREFDTYPE 'Cls2'
%Error: t/t_class_assign_cond_bad.v:22:23: Incompatible types of operands of condition operator: CLASSREFDTYPE 'Cls1' and CLASSREFDTYPE 'Cls2'
: ... note: In instance 't'
22 | c1 = (c1 != null) ? c1 : c2;
| ^
22 | c1 = (c1 != null) ? c1 : c2;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_class_assign_cond_bad.v:23:10: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2'
%Error: t/t_class_assign_cond_bad.v:23:8: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2'
: ... note: In instance 't'
23 | c1 = (c1 != null) ? c2 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:24:23: Incompatible types of operands of condition operator: BASICDTYPE 'logic' and CLASSREFDTYPE 'Cls2'
: ... note: In instance 't'
23 | c1 = (c1 != null) ? c2 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:24:25: Incompatible types of operands of condition operator: BASICDTYPE 'logic' and CLASSREFDTYPE 'Cls2'
24 | c2 = (c1 == null) ? 1'b1 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:24:8: Assign RHS expects a CLASSREFDTYPE 'Cls2', got BASICDTYPE 'logic'
: ... note: In instance 't'
24 | c2 = (c1 == null) ? 1'b1 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:25:27: Incompatible types of operands of condition operator: CLASSREFDTYPE 'ExtCls1' and CLASSREFDTYPE 'Cls1'
: ... note: In instance 't'
24 | c2 = (c1 == null) ? 1'b1 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:24:10: Assign RHS expects a CLASSREFDTYPE 'Cls2', got BASICDTYPE 'logic'
: ... note: In instance 't'
24 | c2 = (c1 == null) ? 1'b1 : c2;
| ^
%Error: t/t_class_assign_cond_bad.v:25:29: Incompatible types of operands of condition operator: CLASSREFDTYPE 'ExtCls1' and CLASSREFDTYPE 'Cls1'
: ... note: In instance 't'
25 | ext_c1 = (c1 == null) ? ext_c1 : c1;
| ^
25 | ext_c1 = (c1 == null) ? ext_c1 : c1;
| ^
%Error: Exiting due to

18
test_regress/t/t_class_assign_cond_bad.v
View File

@ -14,14 +14,14 @@ class ExtCls1;
endclass
module t;
Cls1 c1;
Cls2 c2;
ExtCls1 ext_c1;
Cls1 c1;
Cls2 c2;
ExtCls1 ext_c1;
initial begin
c1 = (c1 != null) ? c1 : c2;
c1 = (c1 != null) ? c2 : c2;
c2 = (c1 == null) ? 1'b1 : c2;
ext_c1 = (c1 == null) ? ext_c1 : c1;
end
initial begin
c1 = (c1 != null) ? c1 : c2;
c1 = (c1 != null) ? c2 : c2;
c2 = (c1 == null) ? 1'b1 : c2;
ext_c1 = (c1 == null) ? ext_c1 : c1;
end
endmodule

74
test_regress/t/t_class_capitalization.v
View File

@ -6,59 +6,59 @@
// Test different uppercase/lowercase capitalization cases
class ClsMixed;
int m;
int M;
int m;
int M;
endclass
class Clsmixed;
int m;
int M;
int m;
int M;
endclass
module ModMixed;
// verilator no_inline_module
int m;
int M;
// verilator no_inline_module
int m;
int M;
endmodule
module Modmixed;
// verilator no_inline_module
int m;
int M;
// verilator no_inline_module
int m;
int M;
endmodule
module t;
// verilator no_inline_module
// verilator no_inline_module
ModMixed modMixed();
Modmixed modmixed();
ModMixed modMixed ();
Modmixed modmixed ();
initial begin
ClsMixed clsMixed;
Clsmixed clsmixed;
initial begin
ClsMixed clsMixed;
Clsmixed clsmixed;
clsMixed = new;
clsMixed.m = 1;
clsMixed.M = 2;
clsmixed = new;
clsmixed.m = 3;
clsmixed.M = 4;
if (clsMixed.m != 1) $stop;
if (clsMixed.M != 2) $stop;
if (clsmixed.m != 3) $stop;
if (clsmixed.M != 4) $stop;
clsMixed = new;
clsMixed.m = 1;
clsMixed.M = 2;
clsmixed = new;
clsmixed.m = 3;
clsmixed.M = 4;
if (clsMixed.m != 1) $stop;
if (clsMixed.M != 2) $stop;
if (clsmixed.m != 3) $stop;
if (clsmixed.M != 4) $stop;
modMixed.m = 1;
modMixed.M = 2;
modmixed.m = 3;
modmixed.M = 4;
if (modMixed.m != 1) $stop;
if (modMixed.M != 2) $stop;
if (modmixed.m != 3) $stop;
if (modmixed.M != 4) $stop;
modMixed.m = 1;
modMixed.M = 2;
modmixed.m = 3;
modmixed.M = 4;
if (modMixed.m != 1) $stop;
if (modMixed.M != 2) $stop;
if (modmixed.m != 3) $stop;
if (modmixed.M != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

46
test_regress/t/t_class_class.v
View File

@ -6,33 +6,35 @@
// Note UVM internals do not require classes-in-classes
package P;
class Cls #(type STORE_T=string);
STORE_T imembera;
STORE_T imemberb;
class SubCls;
class Cls #(
type STORE_T = string
);
STORE_T imembera;
STORE_T imemberb;
class SubCls;
STORE_T smembera;
STORE_T smemberb;
// TODO put extern function here or in t_class_extern.v to check link
endclass : SubCls
SubCls sc;
endclass : Cls
endclass : SubCls
SubCls sc;
endclass : Cls
endpackage : P
module t;
P::Cls#(int) c;
initial begin
c = new;
c.imembera = 10;
c.imemberb = 20;
c.sc = new;
c.sc.smembera = 30;
c.sc.smemberb = 40;
if (c.imembera != 10) $stop;
if (c.imemberb != 20) $stop;
if (c.sc.smembera != 30) $stop;
if (c.sc.smemberb != 40) $stop;
P::Cls #(int) c;
initial begin
c = new;
c.imembera = 10;
c.imemberb = 20;
c.sc = new;
c.sc.smembera = 30;
c.sc.smemberb = 40;
if (c.imembera != 10) $stop;
if (c.imemberb != 20) $stop;
if (c.sc.smembera != 30) $stop;
if (c.sc.smemberb != 40) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

62
test_regress/t/t_class_compare.v
View File

@ -4,47 +4,49 @@
// SPDX-FileCopyrightText: 2023 Ilya Barkov
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end
// Two checks because == and != may not be derived from each other
`define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0)
`define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1)
// verilog_format: on
class Cls;
class InnerCls;
int j;
endclass
int i;
class InnerCls;
int j;
endclass
int i;
endclass
class ExtendCls extends Cls;
endclass
module t;
initial begin
automatic Cls a = new;
automatic Cls b = new;
automatic ExtendCls ext = new;
automatic Cls::InnerCls ia = new;
automatic Cls::InnerCls ib = new;
automatic ExtendCls::InnerCls iext = new;
`check_ne(a, b)
`check_ne(a, ext)
`check_ne(ext, a)
`check_ne(ia, ib)
`check_ne(ia, iext)
`check_ne(iext, ia)
a = b;
ia = ib;
`check_eq(a, b)
`check_eq(ia, ib)
a = ext;
ia = iext;
`check_eq(a, ext)
`check_eq(ext, a)
`check_eq(ia, iext)
`check_eq(iext, ia)
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
automatic Cls a = new;
automatic Cls b = new;
automatic ExtendCls ext = new;
automatic Cls::InnerCls ia = new;
automatic Cls::InnerCls ib = new;
automatic ExtendCls::InnerCls iext = new;
`check_ne(a, b)
`check_ne(a, ext)
`check_ne(ext, a)
`check_ne(ia, ib)
`check_ne(ia, iext)
`check_ne(iext, ia)
a = b;
ia = ib;
`check_eq(a, b)
`check_eq(ia, ib)
a = ext;
ia = iext;
`check_eq(a, ext)
`check_eq(ext, a)
`check_eq(ia, iext)
`check_eq(iext, ia)
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_class_const.v
View File

@ -5,16 +5,16 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
const int aconst = 10;
static const int astatic = 20;
const int aconst = 10;
static const int astatic = 20;
endclass
module t;
initial begin
automatic Cls c = new;
if (c.aconst !== 10) $stop;
if (Cls::astatic !== 20) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
automatic Cls c = new;
if (c.aconst !== 10) $stop;
if (Cls::astatic !== 20) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

47
test_regress/t/t_class_copy.v
View File

@ -5,33 +5,36 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
int imembera;
function int inc_methoda; imembera += 1; return imembera; endfunction
int imembera;
function int inc_methoda;
imembera += 1;
return imembera;
endfunction
endclass
module t;
initial begin
Cls c1;
Cls c2;
Cls c3;
c1 = new;
c1.imembera = 10;
if (c1.inc_methoda() != 11) $stop;
initial begin
Cls c1;
Cls c2;
Cls c3;
c1 = new;
c1.imembera = 10;
if (c1.inc_methoda() != 11) $stop;
// Assignment
c2 = c1;
if (c1.inc_methoda() != 12) $stop;
if (c2.inc_methoda() != 13) $stop;
if (c1.inc_methoda() != 14) $stop;
// Assignment
c2 = c1;
if (c1.inc_methoda() != 12) $stop;
if (c2.inc_methoda() != 13) $stop;
if (c1.inc_methoda() != 14) $stop;
// Shallow copy
c3 = new c1;
// Shallow copy
c3 = new c1;
if (c1.inc_methoda() != 15) $stop;
if (c3.inc_methoda() != 15) $stop;
if (c1.inc_methoda() != 16) $stop;
if (c1.inc_methoda() != 15) $stop;
if (c3.inc_methoda() != 15) $stop;
if (c1.inc_methoda() != 16) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

36
test_regress/t/t_class_copy2.v
View File

@ -4,33 +4,35 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
class Cls;
bit x = 1;
bit x = 1;
endclass
module t;
Cls obj1;
Cls obj2;
Cls obj1;
Cls obj2;
initial begin
obj1 = new;
`checkh(obj1.x, 1);
initial begin
obj1 = new;
`checkh(obj1.x, 1);
obj1.x = 0;
obj2 = new obj1;
`checkh(obj2.x, 0);
obj1.x = 0;
obj2 = new obj1;
`checkh(obj2.x, 0);
obj2.x = 1;
`checkh(obj1.x, 0);
`checkh(obj2.x, 1);
obj2.x = 1;
`checkh(obj1.x, 0);
`checkh(obj2.x, 1);
obj2.x = 0;
`checkh(obj2.x, 0);
obj2.x = 0;
`checkh(obj2.x, 0);
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_class_copy_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_class_copy_bad.v:19:16: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' than expected 'CLASSREFDTYPE 'Other''
%Error: t/t_class_copy_bad.v:22:14: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' than expected 'CLASSREFDTYPE 'Other''
: ... note: In instance 't'
19 | c1 = new co;
| ^~
22 | c1 = new co;
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

17
test_regress/t/t_class_copy_bad.v
View File

@ -8,14 +8,17 @@ class Other;
endclass
class Cls;
int imembera;
function int inc_methoda; imembera += 1; return imembera; endfunction
int imembera;
function int inc_methoda;
imembera += 1;
return imembera;
endfunction
endclass
module t;
initial begin
Cls c1;
Other co;
c1 = new co; // Bad, incompatible types
end
initial begin
Cls c1;
Other co;
c1 = new co; // Bad, incompatible types
end
endmodule

45
test_regress/t/t_class_defaultparams.v
View File

@ -5,25 +5,38 @@
// SPDX-License-Identifier: CC0-1.0
// verilator lint_off NORETURN
class c0 #(type T= real);
class c0 #(
type T = real
);
static function T f();
endfunction
endclass
class c2 #(type REQ=int, type RSP= int, type IMP=int);
function new (IMP imp);
class c2 #(
type REQ = int,
type RSP = int,
type IMP = int
);
function new(IMP imp);
endfunction
endclass
class c3 #(type REQ, type RSP, type IMP=RSP);
function new (IMP imp);
class c3 #(
type REQ,
type RSP,
type IMP = RSP
);
function new(IMP imp);
endfunction
endclass
class c1 #(type REQ= int, RSP=REQ);
typedef c1 #( REQ , RSP) this_type;
typedef c0 #(this_type) type_id;
class c1 #(
type REQ = int,
RSP = REQ
);
typedef c1#(REQ, RSP) this_type;
typedef c0#(this_type) type_id;
c2 #(REQ, RSP, this_type) c2inst;
function new (string name, int parent);
c2inst = new (this);
function new(string name, int parent);
c2inst = new(this);
endfunction
c3 #(REQ, this_type) c3inst;
@ -42,18 +55,18 @@ interface interf;
endinterface
module t;
// `test
interf interf_inst();
interf interf_inst ();
endmodule
class topc;
// `test
endclass
class paramcl;
endclass: paramcl
endclass : paramcl
class c5;
c1 #(paramcl) seq;
function void f();
seq = c1 #(paramcl)::type_id::f();
endfunction: f
c1 #(paramcl) seq;
function void f();
seq = c1#(paramcl)::type_id::f();
endfunction : f
endclass
c5 c5inst;

70
test_regress/t/t_class_diamond.v
View File

@ -6,54 +6,54 @@
module class_tb ();
interface class Ibase;
pure virtual function int fn();
pure virtual function int fn();
endclass
interface class Ic1 extends Ibase;
pure virtual function int fn1();
pure virtual function int fn1();
endclass
interface class Ic2 extends Ibase;
pure virtual function int fn2();
pure virtual function int fn2();
endclass
interface class Ic3 extends Ic1, Ic2;
endclass
class Cls implements Ic3;
virtual function int fn();
return 10;
endfunction
virtual function int fn1();
return 1;
endfunction
virtual function int fn2();
return 2;
endfunction
virtual function int fn();
return 10;
endfunction
virtual function int fn1();
return 1;
endfunction
virtual function int fn2();
return 2;
endfunction
endclass
initial begin
Cls cls;
Ibase ibase;
Ic1 ic1;
Ic2 ic2;
Ic3 ic3;
cls = new;
if (cls.fn() != 10) $stop;
if (cls.fn1() != 1) $stop;
if (cls.fn2() != 2) $stop;
ibase = cls;
ic1 = cls;
ic2 = cls;
ic3 = cls;
if (ibase.fn() != 10) $stop;
if (ic1.fn() != 10) $stop;
if (ic2.fn() != 10) $stop;
if (ic3.fn() != 10) $stop;
if (ic1.fn1() != 1) $stop;
if (ic2.fn2() != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls cls;
Ibase ibase;
Ic1 ic1;
Ic2 ic2;
Ic3 ic3;
cls = new;
if (cls.fn() != 10) $stop;
if (cls.fn1() != 1) $stop;
if (cls.fn2() != 2) $stop;
ibase = cls;
ic1 = cls;
ic2 = cls;
ic3 = cls;
if (ibase.fn() != 10) $stop;
if (ic1.fn() != 10) $stop;
if (ic2.fn() != 10) $stop;
if (ic3.fn() != 10) $stop;
if (ic1.fn1() != 1) $stop;
if (ic2.fn2() != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

32
test_regress/t/t_class_dict.v
View File

@ -4,27 +4,29 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
class Cls;
int x;
function new(int a);
x = a;
endfunction
int x;
function new(int a);
x = a;
endfunction
endclass
module t;
initial begin
automatic int dict[Cls];
automatic Cls c1 = new(1);
automatic Cls c2 = new(2);
dict[c1] = 1;
dict[c2] = 2;
`checkh(dict[c1], 1);
`checkh(dict[c2], 2);
initial begin
automatic int dict[Cls];
automatic Cls c1 = new(1);
automatic Cls c2 = new(2);
dict[c1] = 1;
dict[c2] = 2;
`checkh(dict[c1], 1);
`checkh(dict[c2], 2);
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

22
test_regress/t/t_class_enum.v
View File

@ -6,14 +6,18 @@
module t;
class Cls;
typedef enum {A = 10, B = 20, C = 30} en_t;
endclass
class Cls;
typedef enum {
A = 10,
B = 20,
C = 30
} en_t;
endclass
initial begin
Cls c;
if (c.A != 10) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
if (c.A != 10) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

36
test_regress/t/t_class_eq.v
View File

@ -6,27 +6,27 @@
module t;
class A;
int num;
function new(int num);
class A;
int num;
function new(int num);
this.num = num;
endfunction
endclass
endfunction
endclass
class B;
static A obj = new(2);
endclass
class B;
static A obj = new(2);
endclass
class C;
static A obj = new(5);
endclass
class C;
static A obj = new(5);
endclass
initial begin
#1;
$display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj));
if (B::obj == C::obj) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
#1;
$display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj));
if (B::obj == C::obj) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

56
test_regress/t/t_class_extends.v
View File

@ -7,55 +7,57 @@
typedef class Cls;
class Base0;
// No members to check that to_string handles this
// No members to check that to_string handles this
endclass
class Base1 extends Base0;
int b1member;
typedef int T;
int b1member;
typedef int T;
endclass
class Base2 extends Base1;
int b2member;
int b2member;
endclass
class Cls extends Base2;
int imembera;
int imemberb;
T imemberc;
int imembera;
int imemberb;
T imemberc;
endclass : Cls
class uvm_object_wrapper;
function int create ();
function int create();
return 0;
endfunction
endclass
class uvm__registry #(type T=int) extends uvm_object_wrapper;
class uvm__registry #(
type T = int
) extends uvm_object_wrapper;
// This override must be in the new symbol table, not
// under the extend's symbol table
function int create ();
function int create();
T obj;
return 0;
endfunction
endclass
module t;
initial begin
Cls c;
c = new;
c.b1member = 10;
c.b2member = 30;
c.imembera = 100;
c.imemberb = 110;
c.imemberc = 120;
$display("Display: set = \"%p\"", c); // '{all 4 members}
if (c.b1member != 10) $stop;
if (c.b2member != 30) $stop;
if (c.imembera != 100) $stop;
if (c.imemberb != 110) $stop;
if (c.imemberc != 120) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
c = new;
c.b1member = 10;
c.b2member = 30;
c.imembera = 100;
c.imemberb = 110;
c.imemberc = 120;
$display("Display: set = \"%p\"", c); // '{all 4 members}
if (c.b1member != 10) $stop;
if (c.b2member != 30) $stop;
if (c.imembera != 100) $stop;
if (c.imemberb != 110) $stop;
if (c.imemberc != 120) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

138
test_regress/t/t_class_extends1.v
View File

@ -5,84 +5,88 @@
// SPDX-License-Identifier: CC0-1.0
class Base0;
class BaseInnerOnly;
int inneronly;
function new();
inneronly = 10;
if (inneronly != 10) $stop;
endfunction
endclass
class BaseInnerOnly;
int inneronly;
function new();
inneronly = 10;
if (inneronly != 10) $stop;
endfunction
endclass
class BaseInnerOver;
int innerover;
function new();
innerover = 10;
if (innerover != 10) $stop;
endfunction
endclass
class BaseInnerOver;
int innerover;
function new();
innerover = 10;
if (innerover != 10) $stop;
endfunction
endclass
int baseonly;
int baseover;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
int baseonly;
int baseover;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
function void b_set_bo(int v); baseover = v; endfunction
function int b_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void b_set_io(int v); innerover.innerover = v; endfunction
function int b_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: off
function void b_set_bo(int v); baseover = v; endfunction
function int b_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void b_set_io(int v); innerover.innerover = v; endfunction
function int b_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: on
endclass
class Ext extends Base0;
class BaseInnerOver;
int innerover;
function new();
innerover = 20;
if (innerover != 20) $stop;
endfunction
endclass
class BaseInnerOver;
int innerover;
function new();
innerover = 20;
if (innerover != 20) $stop;
endfunction
endclass
int baseover;
int extonly;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
int baseover;
int extonly;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
function void e_set_bo(int v); baseover = v; endfunction
function int e_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void e_set_io(int v); innerover.innerover = v; endfunction
function int e_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: off
function void e_set_bo(int v); baseover = v; endfunction
function int e_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void e_set_io(int v); innerover.innerover = v; endfunction
function int e_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: on
endclass
module t;
initial begin
Ext c;
c = new;
c.baseonly = 10;
c.baseover = 20;
c.extonly = 30;
c.inneronly.inneronly = 40;
c.innerover.innerover = 50;
if (c.baseonly != 10) $stop;
if (c.baseover != 20) $stop;
if (c.extonly != 30) $stop;
if (c.inneronly.inneronly != 40) $stop;
if (c.innerover.innerover != 50) $stop;
initial begin
Ext c;
c = new;
c.baseonly = 10;
c.baseover = 20;
c.extonly = 30;
c.inneronly.inneronly = 40;
c.innerover.innerover = 50;
if (c.baseonly != 10) $stop;
if (c.baseover != 20) $stop;
if (c.extonly != 30) $stop;
if (c.inneronly.inneronly != 40) $stop;
if (c.innerover.innerover != 50) $stop;
c.b_set_bo(100);
c.e_set_bo(200);
c.b_set_io(300);
c.e_set_io(400);
if (c.b_get_bo() != 100) $stop;
if (c.e_get_bo() != 200) $stop;
if (c.get_bo() != 200) $stop;
if (c.b_get_io() != 300) $stop;
if (c.e_get_io() != 400) $stop;
if (c.get_io() != 400) $stop;
c.b_set_bo(100);
c.e_set_bo(200);
c.b_set_io(300);
c.e_set_io(400);
if (c.b_get_bo() != 100) $stop;
if (c.e_get_bo() != 200) $stop;
if (c.get_bo() != 200) $stop;
if (c.b_get_io() != 300) $stop;
if (c.e_get_io() != 400) $stop;
if (c.get_io() != 400) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

142
test_regress/t/t_class_extends2.v
View File

@ -5,35 +5,37 @@
// SPDX-License-Identifier: CC0-1.0
package Pkg;
class Base0;
class BaseInnerOnly;
int inneronly;
function new();
inneronly = 10;
if (inneronly != 10) $stop;
endfunction
endclass
class Base0;
class BaseInnerOnly;
int inneronly;
function new();
inneronly = 10;
if (inneronly != 10) $stop;
endfunction
endclass
class BaseInnerOver;
int innerover;
function new();
innerover = 10;
if (innerover != 10) $stop;
endfunction
endclass
class BaseInnerOver;
int innerover;
function new();
innerover = 10;
if (innerover != 10) $stop;
endfunction
endclass
int baseonly;
int baseover;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
int baseonly;
int baseover;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
function void b_set_bo(int v); baseover = v; endfunction
function int b_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void b_set_io(int v); innerover.innerover = v; endfunction
function int b_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
endclass
// verilog_format: off
function void b_set_bo(int v); baseover = v; endfunction
function int b_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void b_set_io(int v); innerover.innerover = v; endfunction
function int b_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: on
endclass
endpackage
// We need to import Base0, as verilator currently doesn't support
@ -41,53 +43,55 @@ endpackage
// `BaseInnerOnly` class inside `Ext` class.
import Pkg::Base0;
class Ext extends Pkg::Base0;
class BaseInnerOver;
int innerover;
function new();
innerover = 20;
if (innerover != 20) $stop;
endfunction
endclass
int baseover;
int extonly;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
class BaseInnerOver;
int innerover;
function new();
innerover = 20;
if (innerover != 20) $stop;
endfunction
endclass
int baseover;
int extonly;
BaseInnerOnly inneronly = new;
BaseInnerOver innerover = new;
function void e_set_bo(int v); baseover = v; endfunction
function int e_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void e_set_io(int v); innerover.innerover = v; endfunction
function int e_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: off
function void e_set_bo(int v); baseover = v; endfunction
function int e_get_bo(); return baseover; endfunction
function int get_bo(); return baseover; endfunction
function void e_set_io(int v); innerover.innerover = v; endfunction
function int e_get_io(); return innerover.innerover; endfunction
function int get_io(); return innerover.innerover; endfunction
// verilog_format: on
endclass
module t;
initial begin
Ext c;
c = new;
c.baseonly = 10;
c.baseover = 20;
c.extonly = 30;
c.inneronly.inneronly = 40;
c.innerover.innerover = 50;
if (c.baseonly != 10) $stop;
if (c.baseover != 20) $stop;
if (c.extonly != 30) $stop;
if (c.inneronly.inneronly != 40) $stop;
if (c.innerover.innerover != 50) $stop;
initial begin
Ext c;
c = new;
c.baseonly = 10;
c.baseover = 20;
c.extonly = 30;
c.inneronly.inneronly = 40;
c.innerover.innerover = 50;
if (c.baseonly != 10) $stop;
if (c.baseover != 20) $stop;
if (c.extonly != 30) $stop;
if (c.inneronly.inneronly != 40) $stop;
if (c.innerover.innerover != 50) $stop;
c.b_set_bo(100);
c.e_set_bo(200);
c.b_set_io(300);
c.e_set_io(400);
if (c.b_get_bo() != 100) $stop;
if (c.e_get_bo() != 200) $stop;
if (c.get_bo() != 200) $stop;
if (c.b_get_io() != 300) $stop;
if (c.e_get_io() != 400) $stop;
if (c.get_io() != 400) $stop;
c.b_set_bo(100);
c.e_set_bo(200);
c.b_set_io(300);
c.e_set_io(400);
if (c.b_get_bo() != 100) $stop;
if (c.e_get_bo() != 200) $stop;
if (c.get_bo() != 200) $stop;
if (c.b_get_io() != 300) $stop;
if (c.e_get_io() != 400) $stop;
if (c.get_io() != 400) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_class_extends_aliased_real_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_class_extends_aliased_real_bad.v:14:10: Attempting to extend using non-class
: ... note: In instance 't'
14 | bar #(real_t) bar_real_t;
| ^~~~~~
%Error: t/t_class_extends_aliased_real_bad.v:16:9: Attempting to extend using non-class
: ... note: In instance 't'
16 | bar #(real_t) bar_real_t;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

16
test_regress/t/t_class_extends_aliased_real_bad.v
View File

@ -6,14 +6,16 @@
module t;
class bar #(type T) extends T;
endclass
class bar #(
type T
) extends T;
endclass
typedef real real_t;
typedef real real_t;
bar #(real_t) bar_real_t;
bar #(real_t) bar_real_t;
initial begin
$stop;
end
initial begin
$stop;
end
endmodule

46
test_regress/t/t_class_extends_arg.v
View File

@ -4,41 +4,43 @@
// SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
class Base;
int m_s = 2;
function new(int def = 3);
m_s = def;
endfunction
int m_s = 2;
function new(int def = 3);
m_s = def;
endfunction
endclass
class Cls5Exp extends Base(5);
int m_a = 11;
function new(int def = 42); // Explicit new
m_a = def;
endfunction
int m_a = 11;
function new(int def = 42); // Explicit new
m_a = def;
endfunction
endclass
class Cls5Imp extends Base(5);
int m_a = 12;
// Implicit new
int m_a = 12;
// Implicit new
endclass
module t;
Cls5Exp ce;
Cls5Imp ci;
Cls5Exp ce;
Cls5Imp ci;
initial begin
ce = new(37);
`checkh(ce.m_s, 5);
`checkh(ce.m_a, 37);
ci = new;
`checkh(ci.m_s, 5);
`checkh(ci.m_a, 12);
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
ce = new(37);
`checkh(ce.m_s, 5);
`checkh(ce.m_a, 37);
ci = new;
`checkh(ci.m_s, 5);
`checkh(ci.m_a, 12);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_class_extends_arg_super_bad.out
View File

@ -1,7 +1,7 @@
%Error: t/t_class_extends_arg_super_bad.v:17:13: Explicit super.new not allowed with class extends arguments (IEEE 1800-2023 8.17)
%Error: t/t_class_extends_arg_super_bad.v:17:11: Explicit super.new not allowed with class extends arguments (IEEE 1800-2023 8.17)
: ... Suggest remove super.new
17 | super.new(33);
| ^~~
17 | super.new(33);
| ^~~
t/t_class_extends_arg_super_bad.v:14:25: ... Location of extends argument(s)
14 | class Cls5 extends Base(5);
| ^

18
test_regress/t/t_class_extends_arg_super_bad.v
View File

@ -5,16 +5,16 @@
// SPDX-License-Identifier: CC0-1.0
class Base;
int m_s = 2;
function new(int def = 3);
m_s = def;
endfunction
int m_s = 2;
function new(int def = 3);
m_s = def;
endfunction
endclass
class Cls5 extends Base(5);
int m_a;
function new(int def = 42);
super.new(33); // Bad, can't super.new with extends args
m_a = def;
endfunction
int m_a;
function new(int def = 42);
super.new(33); // Bad, can't super.new with extends args
m_a = def;
endfunction
endclass

26
test_regress/t/t_class_extends_colon.v
View File

@ -8,12 +8,14 @@ interface class Icempty;
endclass : Icempty
package Pkg;
class Icls1 #(parameter PARAM = 12);
localparam LP1 = 1;
function int getParam();
class Icls1 #(
parameter PARAM = 12
);
localparam LP1 = 1;
function int getParam();
return PARAM;
endfunction
endclass
endfunction
endclass
endpackage
@ -22,14 +24,14 @@ endclass
module t;
Cls12 cp12;
Cls12 cp12;
initial begin
cp12 = new;
if (cp12.getParam() != 12) $stop;
initial begin
cp12 = new;
if (cp12.getParam() != 12) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

30
test_regress/t/t_class_extends_default.v
View File

@ -5,28 +5,28 @@
// SPDX-License-Identifier: CC0-1.0
class Base1;
int s = 2;
function new(int def = 3);
s = def;
endfunction
int s = 2;
function new(int def = 3);
s = def;
endfunction
endclass
class Cls1 extends Base1(default);
// Gets new(int def)
// Gets new(int def)
endclass
module t;
initial begin
Cls1 c1;
Cls1 c5;
c1 = new(57);
if (c1.s !== 57) $stop;
initial begin
Cls1 c1;
Cls1 c5;
c1 = new(57);
if (c1.s !== 57) $stop;
c5 = new;
if (c5.s !== 5) $stop;
c5 = new;
if (c5.s !== 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_class_extends_int_param_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_class_extends_int_param_bad.v:9:23: Attempting to extend using non-class
: ... note: In instance 't'
9 | class Bar #(type T=int) extends T;
| ^~~
%Error: t/t_class_extends_int_param_bad.v:10:16: Attempting to extend using non-class
: ... note: In instance 't'
10 | type T = int
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_class_extends_int_param_bad.v
View File

@ -6,11 +6,13 @@
module t;
class Bar #(type T=int) extends T;
endclass
class Bar #(
type T = int
) extends T;
endclass
initial begin
Bar#() bar;
$stop;
end
initial begin
Bar #() bar;
$stop;
end
endmodule

255
test_regress/t/t_class_extends_param.v
View File

@ -4,145 +4,148 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
);
module t;
class Foo;
class InnerFoo;
int y = 10;
function int get_y;
return y;
endfunction
function int get_30;
return 30;
endfunction
endclass
int x = 1;
InnerFoo foo = new;
function int get_x;
return x;
class Foo;
class InnerFoo;
int y = 10;
function int get_y;
return y;
endfunction
function int get_3;
return 3;
function int get_30;
return 30;
endfunction
function InnerFoo get_foo;
return foo;
endclass
int x = 1;
InnerFoo foo = new;
function int get_x;
return x;
endfunction
function int get_3;
return 3;
endfunction
function InnerFoo get_foo;
return foo;
endfunction
endclass
class Bar #(
type T = Foo
) extends T;
endclass
class Baz;
class InnerFoo;
int y = 20;
function int get_y;
return y;
endfunction
endclass
class Bar #(type T=Foo) extends T;
endclass
class Baz;
class InnerFoo;
int y = 20;
function int get_y;
return y;
endfunction
function int get_40;
return 40;
endfunction
endclass
int x = 2;
InnerFoo foo = new;
function int get_x;
return x;
function int get_40;
return 40;
endfunction
function int get_4;
return 4;
endfunction
function InnerFoo get_foo;
return foo;
endfunction
endclass
endclass
int x = 2;
InnerFoo foo = new;
function int get_x;
return x;
endfunction
function int get_4;
return 4;
endfunction
function InnerFoo get_foo;
return foo;
endfunction
endclass
class ExtendBar extends Bar#();
function int get_x;
return super.get_x();
endfunction
function int get_6;
return 2 * get_3();
endfunction
endclass
class ExtendBar extends Bar #();
function int get_x;
return super.get_x();
endfunction
function int get_6;
return 2 * get_3();
endfunction
endclass
class ExtendBar1 extends Bar #(Foo);
function int get_x;
return super.get_x();
endfunction
function int get_6;
return 2 * get_3();
endfunction
endclass
class ExtendBar1 extends Bar #(Foo);
function int get_x;
return super.get_x();
endfunction
function int get_6;
return 2 * get_3();
endfunction
endclass
class ExtendBarBaz extends Bar #(Baz);
function int get_x;
return super.get_x();
endfunction
function int get_8;
return 2 * get_4();
endfunction
endclass
class ExtendBarBaz extends Bar #(Baz);
function int get_x;
return super.get_x();
endfunction
function int get_8;
return 2 * get_4();
endfunction
endclass
class ExtendExtendBar extends ExtendBar;
function int get_12;
return 4 * get_3();
endfunction
endclass
class ExtendExtendBar extends ExtendBar;
function int get_12;
return 4 * get_3();
endfunction
endclass
class FooDict;
Foo q[int];
endclass
class FooDict;
Foo q[int];
endclass
class ExtendFooDict#(type BASE=FooDict) extends BASE;
function int get_x_of_item(int i);
return q[i].x;
endfunction
function int get_y_of_item(int i);
return q[i].get_foo().get_y();
endfunction
endclass
class ExtendFooDict #(
type BASE = FooDict
) extends BASE;
function int get_x_of_item(int i);
return q[i].x;
endfunction
function int get_y_of_item(int i);
return q[i].get_foo().get_y();
endfunction
endclass
Bar #() bar_foo_i;
Bar #(Baz) bar_baz_i;
ExtendBar extend_bar_i;
ExtendBar1 extend_bar1_i;
ExtendBarBaz extend_bar_baz_i;
ExtendExtendBar extend_extend_bar_i;
ExtendFooDict extend_foo_dict_i;
Bar #() bar_foo_i;
Bar #(Baz) bar_baz_i;
ExtendBar extend_bar_i;
ExtendBar1 extend_bar1_i;
ExtendBarBaz extend_bar_baz_i;
ExtendExtendBar extend_extend_bar_i;
ExtendFooDict extend_foo_dict_i;
initial begin
bar_foo_i = new;
bar_baz_i = new;
extend_bar_i = new;
extend_bar1_i = new;
extend_bar_baz_i = new;
extend_extend_bar_i = new;
extend_foo_dict_i = new;
extend_foo_dict_i.q[1] = new;
initial begin
bar_foo_i = new;
bar_baz_i = new;
extend_bar_i = new;
extend_bar1_i = new;
extend_bar_baz_i = new;
extend_extend_bar_i = new;
extend_foo_dict_i = new;
extend_foo_dict_i.q[1] = new;
if (bar_foo_i.get_x() != 1) $stop;
if (bar_foo_i.get_3() != 3) $stop;
if (bar_foo_i.get_foo().get_y() != 10) $stop;
if (bar_foo_i.get_foo().get_30() != 30) $stop;
if (bar_baz_i.get_x() != 2) $stop;
if (bar_baz_i.get_4() != 4) $stop;
if (bar_baz_i.get_foo().get_y() != 20) $stop;
if (bar_baz_i.get_foo().get_40() != 40) $stop;
if (extend_bar_i.get_x() != 1) $stop;
if (extend_bar_i.get_6() != 6) $stop;
if (extend_bar_i.get_x() != 1) $stop;
if (extend_bar_i.get_6() != 6) $stop;
if (extend_bar1_i.get_x() != 1) $stop;
if (extend_bar1_i.get_6() != 6) $stop;
if (extend_bar_baz_i.get_x() != 2) $stop;
if (extend_bar_baz_i.get_8() != 8) $stop;
if (extend_extend_bar_i.get_x() != 1) $stop;
if (extend_extend_bar_i.get_12() != 12) $stop;
if (extend_foo_dict_i.get_x_of_item(1) != 1) $stop;
if (extend_foo_dict_i.get_y_of_item(1) != 10) $stop;
if (bar_foo_i.get_x() != 1) $stop;
if (bar_foo_i.get_3() != 3) $stop;
if (bar_foo_i.get_foo().get_y() != 10) $stop;
if (bar_foo_i.get_foo().get_30() != 30) $stop;
if (bar_baz_i.get_x() != 2) $stop;
if (bar_baz_i.get_4() != 4) $stop;
if (bar_baz_i.get_foo().get_y() != 20) $stop;
if (bar_baz_i.get_foo().get_40() != 40) $stop;
if (extend_bar_i.get_x() != 1) $stop;
if (extend_bar_i.get_6() != 6) $stop;
if (extend_bar_i.get_x() != 1) $stop;
if (extend_bar_i.get_6() != 6) $stop;
if (extend_bar1_i.get_x() != 1) $stop;
if (extend_bar1_i.get_6() != 6) $stop;
if (extend_bar_baz_i.get_x() != 2) $stop;
if (extend_bar_baz_i.get_8() != 8) $stop;
if (extend_extend_bar_i.get_x() != 1) $stop;
if (extend_extend_bar_i.get_12() != 12) $stop;
if (extend_foo_dict_i.get_x_of_item(1) != 1) $stop;
if (extend_foo_dict_i.get_y_of_item(1) != 10) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_class_extends_param_unused.v
View File

@ -4,12 +4,14 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
class Foo#(type T = logic) extends T;
class Foo #(
type T = logic
) extends T;
endclass
module t;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

4
test_regress/t/t_class_extends_rec_bad.v
View File

@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
class RecursiveExtCls extends RecursiveExtCls;
int i;
int i;
endclass
module t;
RecursiveExtCls cls = new;
RecursiveExtCls cls = new;
endmodule

118
test_regress/t/t_class_extends_this.v
View File

@ -7,73 +7,73 @@
typedef class Cls;
class Base;
class BaseInner;
int value = 10;
function void test;
if (value != 10) $stop;
if (this.value != 10) $stop;
value = 20;
if (value != 20) $stop;
this.value = 30;
if (value != 30) $stop;
endfunction
endclass
class BaseInner;
int value = 10;
function void test;
if (value != 10) $stop;
if (this.value != 10) $stop;
value = 20;
if (value != 20) $stop;
this.value = 30;
if (value != 30) $stop;
endfunction
endclass
int value = 1;
BaseInner inner = new;
function void test;
if (value != 1) $stop;
if (this.value != 1) $stop;
value = 2;
if (value != 2) $stop;
this.value = 3;
if (value != 3) $stop;
endfunction
int value = 1;
BaseInner inner = new;
function void test;
if (value != 1) $stop;
if (this.value != 1) $stop;
value = 2;
if (value != 2) $stop;
this.value = 3;
if (value != 3) $stop;
endfunction
endclass
class Cls extends Base;
class BaseInner extends Base::BaseInner;
int value = 100;
function void test;
if (value != 100) $stop;
if (this.value != 100) $stop;
if (super.value != 10) $stop;
super.test();
if (value != 100) $stop;
if (this.value != 100) $stop;
if (super.value != 30) $stop;
value = 200;
if (value != 200) $stop;
this.value = 300;
if (value != 300) $stop;
endfunction
endclass
int value = 20;
BaseInner inner = new;
function void test;
if (value != 20) $stop;
if (this.value != 20) $stop;
if (super.value != 1) $stop;
class BaseInner extends Base::BaseInner;
int value = 100;
function void test;
if (value != 100) $stop;
if (this.value != 100) $stop;
if (super.value != 10) $stop;
super.test();
if (this.value != 20) $stop;
if (value != 100) $stop;
if (this.value != 100) $stop;
if (super.value != 30) $stop;
value = 200;
if (value != 200) $stop;
this.value = 300;
if (value != 300) $stop;
endfunction
endclass
super.value = 9;
this.value = 29;
if (super.value != 9) $stop;
if (value != 29) $stop;
int value = 20;
BaseInner inner = new;
function void test;
if (value != 20) $stop;
if (this.value != 20) $stop;
if (super.value != 1) $stop;
inner.test();
endfunction
super.test();
if (this.value != 20) $stop;
super.value = 9;
this.value = 29;
if (super.value != 9) $stop;
if (value != 29) $stop;
inner.test();
endfunction
endclass
module t;
initial begin
Cls c;
c = new;
c.test();
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
c = new;
c.test();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

50
test_regress/t/t_class_extends_this3.v
View File

@ -7,35 +7,35 @@
typedef class Cls;
class Base;
class Inner;
int value = 10;
function void testBaseInner;
if (value != 10) $stop;
endfunction
endclass
int value = 1;
Inner inner = new;
function void testBase;
if (value != 1) $stop;
if (inner.value != 10) $stop;
endfunction
class Inner;
int value = 10;
function void testBaseInner;
if (value != 10) $stop;
endfunction
endclass
int value = 1;
Inner inner = new;
function void testBase;
if (value != 1) $stop;
if (inner.value != 10) $stop;
endfunction
endclass
class Cls extends Base;
function void testDerived;
if (value != 1) $stop;
if (inner.value != 10) $stop;
endfunction
function void testDerived;
if (value != 1) $stop;
if (inner.value != 10) $stop;
endfunction
endclass
module t;
initial begin
Cls c;
c = new;
c.testBase();
c.testDerived();
c.inner.testBaseInner();
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
c = new;
c.testBase();
c.testDerived();
c.inner.testBaseInner();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_class_extends_vsyment.v
View File

@ -8,8 +8,8 @@ class Foo;
endclass
class Bar extends Foo;
int m_field = get_1();
function int get_1();
return 1;
endfunction
int m_field = get_1();
function int get_1();
return 1;
endfunction
endclass

110
test_regress/t/t_class_extern.v
View File

@ -5,104 +5,104 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern function ext_f_imp(in);
extern static function int get_1();
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
class SubCls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern static function int get_10();
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
endclass
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern function ext_f_imp(in);
extern static function int get_1();
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
class SubCls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern function int ext_f_i(int in);
extern static function int get_10();
extern task ext_t_np;
extern task ext_t_p();
extern task ext_t_i(int in);
endclass
endclass
function int Cls::ext_f_np;
return 1;
return 1;
endfunction
function int Cls::ext_f_p();
return value;
return value;
endfunction
function int Cls::ext_f_i(int in);
return in+1;
return in+1;
endfunction
function Cls::ext_f_imp(in);
return ~in;
return ~in;
endfunction
function int Cls::get_1();
return 1;
return 1;
endfunction
task Cls::ext_t_np();
$write("*-* All Finished *-*\n");
$write("*-* All Finished *-*\n");
endtask
task Cls::ext_t_p();
$finish;
$finish;
endtask
task Cls::ext_t_i(int in);
if (in != 2) $stop;
value = in;
if (in != 2) $stop;
value = in;
endtask
function int Cls::SubCls::ext_f_np;
return 10;
return 10;
endfunction
function int Cls::SubCls::ext_f_p();
return value;
return value;
endfunction
function int Cls::SubCls::ext_f_i(int in);
return in+10;
return in+10;
endfunction
function int Cls::SubCls::get_10();
return 10;
return 10;
endfunction
task Cls::SubCls::ext_t_np();
$write("Cls::SubCls::ext_t_np\n");
$write("Cls::SubCls::ext_t_np\n");
endtask
task Cls::SubCls::ext_t_p();
$write("Cls::SubCls::ext_t_p\n");
$write("Cls::SubCls::ext_t_p\n");
endtask
task Cls::SubCls::ext_t_i(int in);
if (in != 20) $stop;
value = in;
if (in != 20) $stop;
value = in;
endtask
module t;
initial begin
automatic Cls c = new;
automatic Cls::SubCls subc = new;
c.ext_t_i(2);
if (c.ext_f_np() != 1) $stop;
if (c.ext_f_p() != 2) $stop;
if (c.ext_f_i(10) != 11) $stop;
if (c.ext_f_imp(1'b1) != 1'b0) $stop;
if (Cls::get_1() != 1) $stop;
subc.ext_t_i(20);
if (subc.ext_f_np() != 10) $stop;
if (subc.ext_f_p() != 20) $stop;
if (subc.ext_f_i(11) != 21) $stop;
if (Cls::SubCls::get_10() != 10) $stop;
subc.ext_t_np();
subc.ext_t_p();
c.ext_t_np();
c.ext_t_p();
end
initial begin
automatic Cls c = new;
automatic Cls::SubCls subc = new;
c.ext_t_i(2);
if (c.ext_f_np() != 1) $stop;
if (c.ext_f_p() != 2) $stop;
if (c.ext_f_i(10) != 11) $stop;
if (c.ext_f_imp(1'b1) != 1'b0) $stop;
if (Cls::get_1() != 1) $stop;
subc.ext_t_i(20);
if (subc.ext_f_np() != 10) $stop;
if (subc.ext_f_p() != 20) $stop;
if (subc.ext_f_i(11) != 21) $stop;
if (Cls::SubCls::get_10() != 10) $stop;
subc.ext_t_np();
subc.ext_t_p();
c.ext_t_np();
c.ext_t_p();
end
endmodule

18
test_regress/t/t_class_field_name.v
View File

@ -5,17 +5,17 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
int queue;
int queue;
endclass
module t;
initial begin
automatic Cls cls = new;
cls.queue = 1;
if (cls.queue == 1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
automatic Cls cls = new;
cls.queue = 1;
if (cls.queue == 1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

58
test_regress/t/t_class_forward.v
View File

@ -5,36 +5,36 @@
// SPDX-License-Identifier: CC0-1.0
package P;
typedef class ClsB;
class ClsA;
int imembera;
ClsB b;
endclass
class ClsB;
int imemberb;
ClsA a;
endclass
typedef class ClsB;
class ClsA;
int imembera;
ClsB b;
endclass
class ClsB;
int imemberb;
ClsA a;
endclass
endpackage
module t;
P::ClsA ca;
P::ClsB cb;
initial begin
// Alternate between two versions to make sure we don't
// constant propagate between them.
ca = new;
cb = new;
ca.b = new;
cb.a = new;
ca.imembera = 100;
ca.b.imemberb = 111;
cb.imemberb = 200;
cb.a.imembera = 202;
if (ca.imembera != 100) $stop;
if (ca.b.imemberb != 111) $stop;
if (cb.imemberb != 200) $stop;
if (cb.a.imembera != 202) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
P::ClsA ca;
P::ClsB cb;
initial begin
// Alternate between two versions to make sure we don't
// constant propagate between them.
ca = new;
cb = new;
ca.b = new;
cb.a = new;
ca.imembera = 100;
ca.b.imemberb = 111;
cb.imemberb = 200;
cb.a.imembera = 202;
if (ca.imembera != 100) $stop;
if (ca.b.imemberb != 111) $stop;
if (cb.imemberb != 200) $stop;
if (cb.a.imembera != 202) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

24
test_regress/t/t_class_func_arg_unused.v
View File

@ -6,24 +6,24 @@
package uvm_pkg;
class uvm_reg_field; // extends uvm_object;
function void configure(bit overde, bit is_rand);
class uvm_reg_field; // extends uvm_object;
function void configure(bit overde, bit is_rand);
if (overde) is_rand = 0;
if (!is_rand) ; // value.rand_mode(0);
if (!is_rand); // value.rand_mode(0);
// See issue #4567
endfunction
endclass
endfunction
endclass
endpackage
module t;
initial begin
automatic uvm_pkg::uvm_reg_field c = new;
c.configure(1, 0);
c.configure(0, 0);
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
automatic uvm_pkg::uvm_reg_field c = new;
c.configure(1, 0);
c.configure(0, 0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

30
test_regress/t/t_class_func_dot.v
View File

@ -5,27 +5,27 @@
// SPDX-License-Identifier: CC0-1.0
class Cls_report_object;
string m_msg;
function string get_msg;
return m_msg;
endfunction
string m_msg;
function string get_msg;
return m_msg;
endfunction
endclass
function Cls_report_object get_report_object;
Cls_report_object c;
c = new;
c.m_msg = "hello";
return c;
Cls_report_object c;
c = new;
c.m_msg = "hello";
return c;
endfunction
module t;
string s;
string s;
initial begin
Cls_report_object _local_report_object;
s = get_report_object().get_msg();
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls_report_object _local_report_object;
s = get_report_object().get_msg();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

40
test_regress/t/t_class_func_nvoid_bad.out
View File

@ -1,26 +1,26 @@
%Error: t/t_class_func_nvoid_bad.v:47:11: Cannot call a task/void-function as a function: 'mod_fv'
: ... note: In instance 't'
47 | if (mod_fv() == 10) $stop;
| ^~~~~~
%Error: t/t_class_func_nvoid_bad.v:47:9: Cannot call a task/void-function as a function: 'mod_fv'
: ... note: In instance 't'
47 | if (mod_fv() == 10) $stop;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_class_func_nvoid_bad.v:50:11: Cannot call a task/void-function as a function: 'mod_t'
%Error: t/t_class_func_nvoid_bad.v:50:9: Cannot call a task/void-function as a function: 'mod_t'
: ... note: In instance 't'
50 | if (mod_t() == 10) $stop;
| ^~~~~
%Error: t/t_class_func_nvoid_bad.v:58:11: Cannot call a task/void-function as a member function: 'fv'
: ... note: In instance 't'
50 | if (mod_t() == 10) $stop;
| ^~~~~
%Error: t/t_class_func_nvoid_bad.v:58:13: Cannot call a task/void-function as a member function: 'fv'
58 | if (c.fv() == 10) $stop;
| ^~
%Error: t/t_class_func_nvoid_bad.v:61:11: Cannot call a task/void-function as a member function: 't'
: ... note: In instance 't'
58 | if (c.fv() == 10) $stop;
| ^~
%Error: t/t_class_func_nvoid_bad.v:61:13: Cannot call a task/void-function as a member function: 't'
61 | if (c.t() == 10) $stop;
| ^
%Error: t/t_class_func_nvoid_bad.v:69:11: Cannot call a task/void-function as a function: 'sfv'
: ... note: In instance 't'
61 | if (c.t() == 10) $stop;
| ^
%Error: t/t_class_func_nvoid_bad.v:69:13: Cannot call a task/void-function as a function: 'sfv'
69 | if (c.sfv() == 10) $stop;
| ^~~
%Error: t/t_class_func_nvoid_bad.v:72:11: Cannot call a task/void-function as a function: 'st'
: ... note: In instance 't'
69 | if (c.sfv() == 10) $stop;
| ^~~
%Error: t/t_class_func_nvoid_bad.v:72:13: Cannot call a task/void-function as a function: 'st'
: ... note: In instance 't'
72 | if (c.st() == 10) $stop;
| ^~
72 | if (c.st() == 10) $stop;
| ^~
%Error: Exiting due to

102
test_regress/t/t_class_func_nvoid_bad.v
View File

@ -6,71 +6,71 @@
class Cls;
function int fi();
return 10;
endfunction
function void fv();
endfunction
task t();
endtask
static function int sfi();
return 10;
endfunction
static function void sfv();
endfunction
static task st();
endtask
function int fi();
return 10;
endfunction
function void fv();
endfunction
task t();
endtask
static function int sfi();
return 10;
endfunction
static function void sfv();
endfunction
static task st();
endtask
endclass
module t;
function int mod_fi();
return 10;
endfunction
function void mod_fv();
endfunction
task mod_t();
endtask
function int mod_fi();
return 10;
endfunction
function void mod_fv();
endfunction
task mod_t();
endtask
initial begin
Cls c;
c = new;
initial begin
Cls c;
c = new;
// For test of calling function in void context, see t_func_void_bad.v
// For test of calling function in void context, see t_func_void_bad.v
// Module
if (mod_fi() != 10) $stop; // OK
void'(mod_fi()); // OK
// Module
if (mod_fi() != 10) $stop; // OK
void'(mod_fi()); // OK
mod_fv(); // Warn IGNOREDRETURN
void'(mod_fv()); // OK
if (mod_fv() == 10) $stop; // Bad call of task as function
mod_fv(); // Warn IGNOREDRETURN
void'(mod_fv()); // OK
if (mod_fv() == 10) $stop; // Bad call of task as function
mod_t(); // OK
if (mod_t() == 10) $stop; // Bad call of task as function
mod_t(); // OK
if (mod_t() == 10) $stop; // Bad call of task as function
// Member functions
if (c.fi() != 10) $stop; // OK
void'(c.fi()); // OK
// Member functions
if (c.fi() != 10) $stop; // OK
void'(c.fi()); // OK
c.fv(); // Ok
void'(c.fv()); // OK
if (c.fv() == 10) $stop; // Bad
c.fv(); // Ok
void'(c.fv()); // OK
if (c.fv() == 10) $stop; // Bad
c.t(); // OK
if (c.t() == 10) $stop; // Bad
c.t(); // OK
if (c.t() == 10) $stop; // Bad
// Static member functions
if (c.sfi() != 10) $stop; // OK
void'(c.sfi()); // OK
// Static member functions
if (c.sfi() != 10) $stop; // OK
void'(c.sfi()); // OK
c.sfv(); // Ok
void'(c.sfv()); // OK
if (c.sfv() == 10) $stop; // Bad
c.sfv(); // Ok
void'(c.sfv()); // OK
if (c.sfv() == 10) $stop; // Bad
c.st(); // OK
if (c.st() == 10) $stop; // Bad
c.st(); // OK
if (c.st() == 10) $stop; // Bad
$stop;
end
$stop;
end
endmodule

28
test_regress/t/t_class_fwd_cc.v
View File

@ -5,18 +5,18 @@
// SPDX-License-Identifier: CC0-1.0
package Pkg;
typedef class Fwd;
virtual class Virt;
pure virtual function Fwd get_root();
endclass
class Ext extends Virt;
virtual function Fwd get_root();
return Fwd::m_uvm_get_root();
endfunction
endclass
class Fwd;
static function Fwd m_uvm_get_root();
return null;
endfunction
endclass
typedef class Fwd;
virtual class Virt;
pure virtual function Fwd get_root();
endclass
class Ext extends Virt;
virtual function Fwd get_root();
return Fwd::m_uvm_get_root();
endfunction
endclass
class Fwd;
static function Fwd m_uvm_get_root();
return null;
endfunction
endclass
endpackage

46
test_regress/t/t_class_if_assign.v
View File

@ -5,39 +5,39 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
int x;
function new;
x = 1;
endfunction
int x;
function new;
x = 1;
endfunction
endclass
class ExtendCls extends Cls;
function new;
x = 2;
endfunction
function new;
x = 2;
endfunction
endclass
class AnotherExtendCls extends Cls;
function new;
x = 3;
endfunction
function new;
x = 3;
endfunction
endclass
module t;
initial begin
automatic Cls cls = new;
automatic ExtendCls ext_cls = new;
automatic AnotherExtendCls an_ext_cls = new;
initial begin
automatic Cls cls = new;
automatic ExtendCls ext_cls = new;
automatic AnotherExtendCls an_ext_cls = new;
if (cls.x == 1) cls = ext_cls;
else cls = an_ext_cls;
if (cls.x != 2) $stop;
if (cls.x == 1) cls = ext_cls;
else cls = an_ext_cls;
if (cls.x != 2) $stop;
if (cls.x == 1) cls = ext_cls;
else cls = an_ext_cls;
if (cls.x != 3) $stop;
if (cls.x == 1) cls = ext_cls;
else cls = an_ext_cls;
if (cls.x != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

64
test_regress/t/t_class_imp2.v
View File

@ -6,42 +6,42 @@
module t;
interface class Courier;
pure virtual function void deliver();
endclass
class Person implements Courier;
virtual function void deliver();
$display("slow delivery");
endfunction
endclass
interface class Courier;
pure virtual function void deliver();
endclass
class Person implements Courier;
virtual function void deliver();
$display("slow delivery");
endfunction
endclass
interface class Seats;
pure virtual function int seats();
endclass
interface class Seats;
pure virtual function int seats();
endclass
class Vehicle;
endclass
class Vehicle;
endclass
class Car extends Vehicle implements Courier, Seats;
virtual function void deliver();
$display("fast delivery");
endfunction
virtual function int seats(); return 4; endfunction
endclass
class Car extends Vehicle implements Courier, Seats;
virtual function void deliver();
$display("fast delivery");
endfunction
virtual function int seats(); return 4; endfunction
endclass
class MetaCar extends Car;
endclass
class MetaCar extends Car;
endclass
function void do_delivery(Courier courier);
courier.deliver();
endfunction
function void do_delivery(Courier courier);
courier.deliver();
endfunction
initial begin
MetaCar car;
car = new();
do_delivery(car);
if (car.seats() != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
MetaCar car;
car = new();
do_delivery(car);
if (car.seats() != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

46
test_regress/t/t_class_inc.v
View File

@ -4,34 +4,38 @@
// SPDX-FileCopyrightText: 2023 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
class Base #(type T = integer);
T m_count;
class Base #(
type T = integer
);
T m_count;
function void test1();
if (this.m_count != 0) $stop;
if (this.m_count++ != 0) $stop;
if (this.m_count != 1) $stop;
if (m_count++ != 1) $stop;
if (this.m_count != 2) $stop;
endfunction
function void test1();
if (this.m_count != 0) $stop;
if (this.m_count++ != 0) $stop;
if (this.m_count != 1) $stop;
if (m_count++ != 1) $stop;
if (this.m_count != 2) $stop;
endfunction
endclass
class Cls #(type T = integer) extends Base #(T);
class Cls #(
type T = integer
) extends Base #(T);
endclass
module t;
Cls #(int) c;
Cls #(int) c;
initial begin
c = new;
c.test1();
initial begin
c = new;
c.test1();
c.m_count = 0;
if (c.m_count != 0) $stop;
if (c.m_count++ != 0) $stop;
if (c.m_count != 1) $stop;
c.m_count = 0;
if (c.m_count != 0) $stop;
if (c.m_count++ != 0) $stop;
if (c.m_count != 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

78
test_regress/t/t_class_link_delay.v
View File

@ -4,49 +4,47 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t
(/*AUTOARG*/
// Outputs
someOutput,
// Inputs
clk, reset_l, InOne, InTwo
);
module t ( /*AUTOARG*/
// Outputs
someOutput,
// Inputs
clk,
reset_l,
InOne,
InTwo
);
input clk;
input reset_l;
input InOne, InTwo;
output logic someOutput;
input clk;
input reset_l;
input InOne, InTwo;
output logic someOutput;
typedef enum {
STATE_ONE,
STATE_TWO,
STATE_THREE,
STATE_FOUR
} some_state_t;
typedef enum {
STATE_ONE,
STATE_TWO,
STATE_THREE,
STATE_FOUR
} some_state_t;
some_state_t some_FSM;
some_state_t some_FSM;
always_ff @ (posedge clk or negedge reset_l) begin
if(!reset_l)
some_FSM <= some_FSM.first;
else begin
unique case (some_FSM)
STATE_ONE, STATE_TWO, STATE_THREE: begin
if(InOne & InTwo)
some_FSM <= some_FSM.next;
else if(InOne)
some_FSM <= some_FSM;
else
some_FSM <= some_FSM.first;
end
default: begin
some_FSM <= STATE_ONE;
end
endcase
end
end
always_ff @(posedge clk or negedge reset_l) begin
if (!reset_l) some_FSM <= some_FSM.first;
else begin
unique case (some_FSM)
STATE_ONE, STATE_TWO, STATE_THREE: begin
if (InOne & InTwo) some_FSM <= some_FSM.next;
else if (InOne) some_FSM <= some_FSM;
else some_FSM <= some_FSM.first;
end
default: begin
some_FSM <= STATE_ONE;
end
endcase
end
end
always_comb begin
someOutput = (some_FSM == STATE_FOUR);
end
always_comb begin
someOutput = (some_FSM == STATE_FOUR);
end
endmodule

200
test_regress/t/t_class_local.v
View File

@ -5,18 +5,65 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
typedef enum {A = 10, B = 20, C = 30} en_t;
typedef enum {
A = 10,
B = 20,
C = 30
} en_t;
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = B;
task f_pub; endtask
local task f_loc; endtask
protected task f_prot; endtask
static task s_pub; endtask
static local task s_loc; endtask
static protected task s_prot; endtask
task check;
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = B;
task f_pub;
endtask
local task f_loc;
endtask
protected task f_prot;
endtask
static task s_pub;
endtask
static local task s_loc;
endtask
static protected task s_prot;
endtask
task check;
Cls o;
if (m_pub != 1) $stop;
if (m_loc != 2) $stop;
if (m_prot != 20) $stop;
f_pub(); // Ok
f_loc(); // Ok
f_prot(); // Ok
s_pub(); // Ok
s_loc(); // Ok
s_prot(); // Ok
Cls::s_pub(); // Ok
Cls::s_loc(); // Ok
Cls::s_prot(); // Ok
endtask
class InnerCls;
typedef enum {
A = 10,
B = 20,
C = 30
} en_t;
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = B;
task f_pub;
endtask
local task f_loc;
endtask
protected task f_prot;
endtask
static task s_pub;
endtask
static local task s_loc;
endtask
static protected task s_prot;
endtask
task check;
Cls o;
if (m_pub != 1) $stop;
if (m_loc != 2) $stop;
@ -30,96 +77,69 @@ class Cls;
Cls::s_pub(); // Ok
Cls::s_loc(); // Ok
Cls::s_prot(); // Ok
endtask
class InnerCls;
typedef enum {A = 10, B = 20, C = 30} en_t;
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = B;
task f_pub; endtask
local task f_loc; endtask
protected task f_prot; endtask
static task s_pub; endtask
static local task s_loc; endtask
static protected task s_prot; endtask
task check;
Cls o;
if (m_pub != 1) $stop;
if (m_loc != 2) $stop;
if (m_prot != 20) $stop;
f_pub(); // Ok
f_loc(); // Ok
f_prot(); // Ok
s_pub(); // Ok
s_loc(); // Ok
s_prot(); // Ok
Cls::s_pub(); // Ok
Cls::s_loc(); // Ok
Cls::s_prot(); // Ok
endtask
endclass
endtask
endclass
endclass
class Ext extends Cls;
task check;
task check;
if (m_pub != 1) $stop;
if (m_prot != 20) $stop;
f_pub(); // Ok
f_prot(); // Ok
s_pub(); // Ok
s_prot(); // Ok
Cls::s_pub(); // Ok
Cls::s_prot(); // Ok
endtask
class ExtInner extends Cls::InnerCls;
task check;
if (m_pub != 1) $stop;
if (m_prot != 20) $stop;
f_pub(); // Ok
f_prot(); // Ok
s_pub(); // Ok
s_prot(); // Ok
Cls::s_pub(); // Ok
Cls::s_prot(); // Ok
endtask
class ExtInner extends Cls::InnerCls;
task check;
if (m_pub != 1) $stop;
if (m_prot != 20) $stop;
f_pub(); // Ok
f_prot(); // Ok
s_pub(); // Ok
s_prot(); // Ok
Cls::InnerCls::s_pub(); // Ok
Cls::InnerCls::s_prot(); // Ok
endtask
endclass
Cls::InnerCls::s_pub(); // Ok
Cls::InnerCls::s_prot(); // Ok
endtask
endclass
endclass
module t;
const Cls mod_c = new;
const Cls::InnerCls imod_c = new;
const Cls mod_c = new;
const Cls::InnerCls imod_c = new;
initial begin
Cls c;
Cls::InnerCls i;
Ext e;
Ext::ExtInner ei;
if (c.A != 10) $stop;
if (i.A != 10) $stop;
c = new;
i = new;
e = new;
ei = new;
if (c.m_pub != 1) $stop;
if (i.m_pub != 1) $stop;
//
if (mod_c.A != 10) $stop;
if (imod_c.A != 10) $stop;
//
c.check();
i.check();
e.check();
ei.check();
//
Cls::s_pub(); // Ok
Cls::InnerCls::s_pub(); // Ok
c.s_pub(); // Ok
i.s_pub(); // Ok
e.s_pub(); // Ok
ei.s_pub(); // Ok
//
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
Cls::InnerCls i;
Ext e;
Ext::ExtInner ei;
if (c.A != 10) $stop;
if (i.A != 10) $stop;
c = new;
i = new;
e = new;
ei = new;
if (c.m_pub != 1) $stop;
if (i.m_pub != 1) $stop;
//
if (mod_c.A != 10) $stop;
if (imod_c.A != 10) $stop;
//
c.check();
i.check();
e.check();
ei.check();
//
Cls::s_pub(); // Ok
Cls::InnerCls::s_pub(); // Ok
c.s_pub(); // Ok
i.s_pub(); // Ok
e.s_pub(); // Ok
ei.s_pub(); // Ok
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

196
test_regress/t/t_class_local_bad.out
View File

@ -1,107 +1,107 @@
%Error-ENCAPSULATED: t/t_class_local_bad.v:71:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
%Error-ENCAPSULATED: t/t_class_local_bad.v:72:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
71 | bad(); if (c.m_loc != 2) $stop;
| ^~~~~
t/t_class_local_bad.v:71:20: ... Location of definition
15 | local int m_loc = 2;
| ^~~~~
... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest
%Error-ENCAPSULATED: t/t_class_local_bad.v:72:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
72 | bad(); if (c.m_prot != 20) $stop;
| ^~~~~~
t/t_class_local_bad.v:72:20: ... Location of definition
16 | protected int m_prot = 3;
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:74:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
74 | bad(); if (e.m_loc != 2) $stop;
| ^~~~~
t/t_class_local_bad.v:74:20: ... Location of definition
15 | local int m_loc = 2;
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:75:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
75 | bad(); if (e.m_prot != 20) $stop;
| ^~~~~~
t/t_class_local_bad.v:75:20: ... Location of definition
16 | protected int m_prot = 3;
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:77:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
77 | bad(); c.f_loc();
| ^~~~~
t/t_class_local_bad.v:77:16: ... Location of definition
18 | local task f_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:78:16: 'f_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
78 | bad(); c.f_prot();
| ^~~~~~
t/t_class_local_bad.v:78:16: ... Location of definition
19 | protected task f_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:80:16: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
80 | bad(); c.s_loc();
| ^~~~~
t/t_class_local_bad.v:80:16: ... Location of definition
21 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:81:16: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
81 | bad(); c.s_prot();
| ^~~~~~
t/t_class_local_bad.v:81:16: ... Location of definition
22 | static protected task s_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:83:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
83 | bad(); Cls::s_loc();
| ^~~~~
t/t_class_local_bad.v:83:19: ... Location of definition
21 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:84:19: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
84 | bad(); Cls::s_prot();
| ^~~~~~
t/t_class_local_bad.v:84:19: ... Location of definition
22 | static protected task s_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:47:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
47 | bad(); if (m_loc != 10) $stop;
72 | bad(); if (c.m_loc != 2) $stop;
| ^~~~~
t/t_class_local_bad.v:47:18: ... Location of definition
15 | local int m_loc = 2;
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:50:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
t/t_class_local_bad.v:72:18: ... Location of definition
16 | local int m_loc = 2;
| ^~~~~
... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest
%Error-ENCAPSULATED: t/t_class_local_bad.v:73:18: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
50 | bad(); f_loc();
| ^~~~~
t/t_class_local_bad.v:50:14: ... Location of definition
18 | local task f_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:53:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
73 | bad(); if (c.m_prot != 20) $stop;
| ^~~~~~
t/t_class_local_bad.v:73:18: ... Location of definition
17 | protected int m_prot = 3;
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:75:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
53 | bad(); o.f_loc();
75 | bad(); if (e.m_loc != 2) $stop;
| ^~~~~
t/t_class_local_bad.v:75:18: ... Location of definition
16 | local int m_loc = 2;
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:76:18: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
76 | bad(); if (e.m_prot != 20) $stop;
| ^~~~~~
t/t_class_local_bad.v:76:18: ... Location of definition
17 | protected int m_prot = 3;
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:78:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
78 | bad(); c.f_loc();
| ^~~~~
t/t_class_local_bad.v:78:14: ... Location of definition
19 | local task f_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:79:14: 'f_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
79 | bad(); c.f_prot();
| ^~~~~~
t/t_class_local_bad.v:79:14: ... Location of definition
20 | protected task f_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:81:14: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
81 | bad(); c.s_loc();
| ^~~~~
t/t_class_local_bad.v:81:14: ... Location of definition
22 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:82:14: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
82 | bad(); c.s_prot();
| ^~~~~~
t/t_class_local_bad.v:82:14: ... Location of definition
23 | static protected task s_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:84:17: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
84 | bad(); Cls::s_loc();
| ^~~~~
t/t_class_local_bad.v:84:17: ... Location of definition
22 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:85:17: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
85 | bad(); Cls::s_prot();
| ^~~~~~
t/t_class_local_bad.v:85:17: ... Location of definition
23 | static protected task s_prot; endtask
| ^~~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:48:16: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
48 | bad(); if (m_loc != 10) $stop;
| ^~~~~
t/t_class_local_bad.v:53:16: ... Location of definition
18 | local task f_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:56:14: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
t/t_class_local_bad.v:48:16: ... Location of definition
16 | local int m_loc = 2;
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:51:12: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
56 | bad(); s_loc();
51 | bad(); f_loc();
| ^~~~~
t/t_class_local_bad.v:51:12: ... Location of definition
19 | local task f_loc; endtask
| ^~~~~
t/t_class_local_bad.v:56:14: ... Location of definition
21 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:59:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
%Error-ENCAPSULATED: t/t_class_local_bad.v:54:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
59 | bad(); Cls::s_loc();
| ^~~~~
t/t_class_local_bad.v:59:19: ... Location of definition
21 | static local task s_loc; endtask
| ^~~~~
54 | bad(); o.f_loc();
| ^~~~~
t/t_class_local_bad.v:54:14: ... Location of definition
19 | local task f_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:57:12: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
57 | bad(); s_loc();
| ^~~~~
t/t_class_local_bad.v:57:12: ... Location of definition
22 | static local task s_loc; endtask
| ^~~~~
%Error-ENCAPSULATED: t/t_class_local_bad.v:60:17: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18)
: ... note: In instance 't'
60 | bad(); Cls::s_loc();
| ^~~~~
t/t_class_local_bad.v:60:17: ... Location of definition
22 | static local task s_loc; endtask
| ^~~~~
%Error: Exiting due to

139
test_regress/t/t_class_local_bad.v
View File

@ -10,80 +10,81 @@ endtask
task bad;
endtask
// verilog_format: off
class Cls;
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = 3;
task f_pub; endtask
local task f_loc; endtask
protected task f_prot; endtask
static task s_pub; endtask
static local task s_loc; endtask
static protected task s_prot; endtask
task check;
Cls o;
ok(); if (m_pub != 1) $stop;
ok(); if (m_loc != 10) $stop;
ok(); if (m_prot != 20) $stop;
ok(); f_pub();
ok(); f_loc();
ok(); f_prot();
ok(); o.f_pub();
ok(); o.f_loc();
ok(); o.f_prot();
ok(); s_pub();
ok(); s_loc();
ok(); s_prot();
ok(); Cls::s_pub();
ok(); Cls::s_loc();
ok(); Cls::s_prot();
endtask
int m_pub = 1;
local int m_loc = 2;
protected int m_prot = 3;
task f_pub; endtask
local task f_loc; endtask
protected task f_prot; endtask
static task s_pub; endtask
static local task s_loc; endtask
static protected task s_prot; endtask
task check;
Cls o;
ok(); if (m_pub != 1) $stop;
ok(); if (m_loc != 10) $stop;
ok(); if (m_prot != 20) $stop;
ok(); f_pub();
ok(); f_loc();
ok(); f_prot();
ok(); o.f_pub();
ok(); o.f_loc();
ok(); o.f_prot();
ok(); s_pub();
ok(); s_loc();
ok(); s_prot();
ok(); Cls::s_pub();
ok(); Cls::s_loc();
ok(); Cls::s_prot();
endtask
endclass
class Ext extends Cls;
task check;
Ext o;
ok(); if (m_pub != 1) $stop;
bad(); if (m_loc != 10) $stop;
ok(); if (m_prot != 20) $stop;
ok(); f_pub();
bad(); f_loc();
ok(); f_prot();
ok(); o.f_pub();
bad(); o.f_loc();
ok(); o.f_prot();
ok(); s_pub();
bad(); s_loc();
ok(); s_prot();
ok(); Cls::s_pub();
bad(); Cls::s_loc();
ok(); Cls::s_prot();
endtask
task check;
Ext o;
ok(); if (m_pub != 1) $stop;
bad(); if (m_loc != 10) $stop;
ok(); if (m_prot != 20) $stop;
ok(); f_pub();
bad(); f_loc();
ok(); f_prot();
ok(); o.f_pub();
bad(); o.f_loc();
ok(); o.f_prot();
ok(); s_pub();
bad(); s_loc();
ok(); s_prot();
ok(); Cls::s_pub();
bad(); Cls::s_loc();
ok(); Cls::s_prot();
endtask
endclass
module t;
initial begin
Cls c;
Ext e;
c = new;
e = new;
ok(); if (c.m_pub != 1) $stop;
bad(); if (c.m_loc != 2) $stop;
bad(); if (c.m_prot != 20) $stop;
ok(); if (e.m_pub != 1) $stop;
bad(); if (e.m_loc != 2) $stop;
bad(); if (e.m_prot != 20) $stop;
ok(); c.f_pub();
bad(); c.f_loc();
bad(); c.f_prot();
ok(); c.s_pub();
bad(); c.s_loc();
bad(); c.s_prot();
ok(); Cls::s_pub();
bad(); Cls::s_loc();
bad(); Cls::s_prot();
//
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
Ext e;
c = new;
e = new;
ok(); if (c.m_pub != 1) $stop;
bad(); if (c.m_loc != 2) $stop;
bad(); if (c.m_prot != 20) $stop;
ok(); if (e.m_pub != 1) $stop;
bad(); if (e.m_loc != 2) $stop;
bad(); if (e.m_prot != 20) $stop;
ok(); c.f_pub();
bad(); c.f_loc();
bad(); c.f_prot();
ok(); c.s_pub();
bad(); c.s_loc();
bad(); c.s_prot();
ok(); Cls::s_pub();
bad(); Cls::s_loc();
bad(); Cls::s_prot();
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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