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Fix syntax error on unsupported defparam array (#6915).

This commit is contained in:
Wilson Snyder 2026-01-12 17:34:10 -05:00
parent db8635a8ef
commit a3d0f16185
4 changed files with 94 additions and 63 deletions
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@ -387,6 +387,7 @@ Verilator 5.040 2025-08-30
* Fix wide select expansion and substitution (#6341) (#6345). [Geza Lore]
* Fix upcasting class type parameters (#6344). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix undefined weak link for Apple GCC etc (#6348). [Congcong Cai]
* Fix syntax error on unsupported defparam array (#6915).
Verilator 5.038 2025-07-08

26
src/verilog.y
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@ -3176,11 +3176,27 @@ list_of_defparam_assignments<nodep>: //== IEEE: list_of_defparam_assignments
;
defparam_assignment<nodep>: // ==IEEE: defparam_assignment
idAny '.' idAny '=' expr { $$ = new AstDefParam{$4, *$1, *$3, $5}; }
| idAny '=' expr
{ $$ = nullptr; BBUNSUP($2, "Unsupported: defparam with no dot"); DEL($3); }
| idAny '.' idAny '.'
{ $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot"); }
defparamIdRange '.' defparamIdRange '=' expr
{ $$ = new AstDefParam{$4, *$1, *$3, $5}; }
| defparamIdRange '=' expr
{ $$ = nullptr; BBUNSUP($2, "Unsupported: defparam with no dot");
DEL($3); }
| defparamIdRange '.' defparamIdRange '.' defparamIdRangeList '=' expr
{ $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot");
DEL($7); }
;
defparamIdRangeList<strp>: // IEEE: part of defparam_assignment
defparamIdRange { $$ = $1; }
| defparamIdRangeList '.' defparamIdRange { $$ = $3; }
;
defparamIdRange<strp>: // IEEE: part of defparam_assignment
idAny
{ $$ = $1; }
| idAny part_select_rangeList
{ $$ = $1; BBUNSUP($2, "Unsupported: defparam with arrayed instance");
DEL($2); }
;
//************************************************

31
test_regress/t/t_gen_defparam_multi.out
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@ -1,18 +1,17 @@
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:14:17: Unsupported: defparam with no dot
14 | defparam PAR = 5;
| ^
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:12:16: Unsupported: defparam with no dot
12 | defparam PAR = 5;
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:39:24: Unsupported: defparam with more than one dot
39 | defparam m2.m3.PAR3 = 80;
| ^
%Error: t/t_gen_defparam_multi.v:39:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
39 | defparam m2.m3.PAR3 = 80;
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:44:24: Unsupported: defparam with more than one dot
44 | defparam m2.m3.PAR3 = 40;
| ^
%Error: t/t_gen_defparam_multi.v:44:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
44 | defparam m2.m3.PAR3 = 40;
| ^~~~
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:28:19: Unsupported: defparam with arrayed instance
28 | defparam blk[i].u_m3.PAR3 = i;
| ^
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:28:27: Unsupported: defparam with more than one dot
28 | defparam blk[i].u_m3.PAR3 = i;
| ^
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:51:43: Unsupported: defparam with more than one dot
51 | defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80;
| ^
%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:55:43: Unsupported: defparam with more than one dot
55 | defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40;
| ^
%Error: Exiting due to

99
test_regress/t/t_gen_defparam_multi.v
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@ -4,56 +4,71 @@
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter PAR = 3;
module t (
input clk
);
parameter PAR = 3;
defparam PAR = 5;
defparam PAR = 5;
wire [31:0] o2a, o2b, o3a, o3b;
wire [31:0] o2a, o2b, o3a, o3b;
m1 #(0) m1a(.o2(o2a), .o3(o3a));
m1 #(1) m1b(.o2(o2b), .o3(o3b));
m1 #(0) m1a (
.o2(o2a),
.o3(o3a)
);
m1 #(1) m1b (
.o2(o2b),
.o3(o3b)
);
always @ (posedge clk) begin
if (PAR != 5) $stop;
if (o2a != 8) $stop;
if (o2b != 4) $stop;
if (o3a != 80) $stop;
if (o3b != 40) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
generate
for (genvar i = 0; i < 8; i = i + 1) begin : blk
m3 u_m3 ();
defparam blk[i].u_m3.PAR3 = i;
end
endgenerate
always @(posedge clk) begin
if (PAR != 5) $stop;
if (o2a != 8) $stop;
if (o2b != 4) $stop;
if (o3a != 80) $stop;
if (o3b != 40) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module m1 (output wire [31:0] o2,
output wire [31:0] o3);
parameter W = 0;
generate
if (W == 0) begin
m2 m2 (.*);
defparam m2.PAR2 = 8;
defparam m2.m3.PAR3 = 80;
end
else begin
m2 m2 (.*);
defparam m2.PAR2 = 4;
defparam m2.m3.PAR3 = 40;
end
endgenerate
module m1 (
output wire [31:0] o2,
output wire [31:0] o3
);
parameter W = 0;
generate
if (W == 0) begin
m2 m2 (.*);
defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80;
end
else begin
m2 m2 (.*);
defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40;
end
endgenerate
endmodule
module m2 (output wire [31:0] o2,
output wire [31:0] o3);
parameter PAR2 = 20;
assign o2 = PAR2;
m3 m3 (.*);
module m2 (
output wire [31:0] o2,
output wire [31:0] o3
);
parameter PAR2 = 20;
assign o2 = PAR2;
m3 m3 (.*);
endmodule
module m3 (output wire [31:0] o3);
parameter PAR3 = 40;
assign o3 = PAR3;
module m3 (
output wire [31:0] o3
);
parameter PAR3 = 40;
assign o3 = PAR3;
endmodule