Tests: Reindent some tests. No functional change.
This commit is contained in:
Wilson Snyder
parent
59bc4cf66b
commit
03e5c3b2ff
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@ -14,51 +14,51 @@
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t ();
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timeunit 10ns;
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timeprecision 1ns;
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module t;
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timeunit 10ns;
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timeprecision 1ns;
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longint should_be_2, should_be_3;
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real should_be_1p6, should_be_3p2;
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longint should_be_2, should_be_3;
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real should_be_1p6, should_be_3p2;
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initial begin : initial_blk1
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should_be_2 = 0;
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should_be_3 = 0;
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#(16ns);
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$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
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should_be_2 = $time();
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should_be_1p6 = $realtime();
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#(16ns);
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$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
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should_be_3 = $time();
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should_be_3p2 = $realtime();
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#(16ns);
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$finish(1);
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end
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initial begin : initial_blk2
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#(100ns);
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$display("%%Error: We should not get here");
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$stop;
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initial begin : initial_blk1
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should_be_2 = 0;
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should_be_3 = 0;
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#(16ns);
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$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
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should_be_2 = $time();
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should_be_1p6 = $realtime();
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#(16ns);
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$display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime());
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should_be_3 = $time();
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should_be_3p2 = $realtime();
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#(16ns);
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$finish(1);
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end
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function bit real_chk(input real tvar, input real evar);
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real diff;
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diff = tvar - evar;
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return (diff < 1e-9) && (diff > -1e-9);
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endfunction
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initial begin : initial_blk2
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#(100ns);
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$display("%%Error: We should not get here");
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$stop;
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end
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final begin : last_blk
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$display("Info: should_be_2 = %0d", should_be_2);
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$display("Info: should_be_3 = %0d", should_be_3);
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`checkd(should_be_2, 2);
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`checkd(should_be_3, 3);
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function bit real_chk(input real tvar, input real evar);
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real diff;
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diff = tvar - evar;
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return (diff < 1e-9) && (diff > -1e-9);
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endfunction
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chk_2 : assert(should_be_2 == 2);
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chk_3 : assert(should_be_3 == 3);
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chk_1p6 : assert(real_chk(should_be_1p6, 1.6));
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chk_3p2 : assert(real_chk(should_be_3p2, 3.2));
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$write("*-* All Finished *-*\n");
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end
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final begin : last_blk
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$display("Info: should_be_2 = %0d", should_be_2);
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$display("Info: should_be_3 = %0d", should_be_3);
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`checkd(should_be_2, 2);
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`checkd(should_be_3, 3);
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chk_2 : assert(should_be_2 == 2);
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chk_3 : assert(should_be_3 == 3);
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chk_1p6 : assert(real_chk(should_be_1p6, 1.6));
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chk_3p2 : assert(real_chk(should_be_3p2, 3.2));
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$write("*-* All Finished *-*\n");
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end
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endmodule
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@ -10,24 +10,24 @@
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`timescale 1ns/1ps
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module t;
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time t;
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time t;
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// realtime value scaled to timeunit, rounded to timeprecision
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initial begin
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// verilator lint_off REALCVT
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t = 1s; `checkd(t, 64'd1000000000);
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t = 2ms; `checkd(t, 2000000);
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t = 1ms; `checkd(t, 1000000);
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t = 1us; `checkd(t, 1000);
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t = 1ns; `checkd(t, 1);
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t = 1ps; `checkd(t, 0); // Below precision
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t = 1fs; `checkd(t, 0);
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// realtime value scaled to timeunit, rounded to timeprecision
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initial begin
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// verilator lint_off REALCVT
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t = 1s; `checkd(t, 64'd1000000000);
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t = 2ms; `checkd(t, 2000000);
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t = 1ms; `checkd(t, 1000000);
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t = 1us; `checkd(t, 1000);
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t = 1ns; `checkd(t, 1);
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t = 1ps; `checkd(t, 0); // Below precision
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t = 1fs; `checkd(t, 0);
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t = 2.3ps; `checkd(t, 0);
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t = 2.4us; `checkd(t, 2400);
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// verilator lint_on REALCVT
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t = 2.3ps; `checkd(t, 0);
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t = 2.4us; `checkd(t, 2400);
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// verilator lint_on REALCVT
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$write("*-* All Finished *-*\n");
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$finish;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -4,36 +4,34 @@
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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`timescale 1ns / 1ps
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module vip_snitch_cluster
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#(parameter realtime ClkPeriod = 10ns)
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(output logic clk_o);
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module vip_snitch_cluster #(
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parameter realtime ClkPeriod = 10ns
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) (
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output logic clk_o
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);
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initial begin
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forever begin
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clk_o = 1;
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#(ClkPeriod/2);
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clk_o = 0;
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#(ClkPeriod/2);
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end
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end
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initial begin
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forever begin
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clk_o = 1;
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#(ClkPeriod / 2);
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clk_o = 0;
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#(ClkPeriod / 2);
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end
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end
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initial begin
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#(ClkPeriod*100);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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#(ClkPeriod * 100);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module t;
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logic clk;
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logic clk;
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vip_snitch_cluster #(
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.ClkPeriod(1ns)
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) vip (
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.clk_o(clk)
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);
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vip_snitch_cluster #(.ClkPeriod(1ns)) vip (.clk_o(clk));
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endmodule
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@ -4,61 +4,63 @@
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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`timescale 1ns / 1ps
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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integer cyc = 0;
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time in;
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// verilator lint_off REALCVT
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initial in = 5432109876.543210ns; // Will round to time units
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// verilator lint_on REALCVT
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time in;
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// verilator lint_off REALCVT
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initial in = 5432109876.543210ns; // Will round to time units
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// verilator lint_on REALCVT
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// This shows time changes when passed between modules with different units
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// See also discussion in uvm_tlm2_time.svh
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// This shows time changes when passed between modules with different units
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// See also discussion in uvm_tlm2_time.svh
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ps ps (.*);
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ns ns (.*);
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ps ps (.*);
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ns ns (.*);
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 60) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 60) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`timescale 1ps/1ps
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`timescale 1ps / 1ps
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module ps
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(input clk,
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input integer cyc,
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input time in);
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module ps (
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input clk,
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input integer cyc,
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input time in
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);
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always @ (posedge clk) begin
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if (cyc == 10) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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always @(posedge clk) begin
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if (cyc == 10) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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endmodule
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`timescale 1ns/1ps
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`timescale 1ns / 1ps
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module ns
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(input clk,
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input integer cyc,
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input time in);
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module ns (
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input clk,
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input integer cyc,
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input time in
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);
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always @ (posedge clk) begin
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if (cyc == 20) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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always @(posedge clk) begin
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if (cyc == 20) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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endmodule
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@ -6,34 +6,33 @@
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module t;
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timeunit 1ns;
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timeprecision 1ps;
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timeunit 1ns; timeprecision 1ps;
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time t;
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time t;
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initial begin
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t = 10ns;
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initial begin
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t = 10ns;
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$write("[%0t] In %m: Hi\n", $time);
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$printtimescale;
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$printtimescale();
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$printtimescale(t);
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$write("[%0t] In %m: Hi\n", $time);
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$printtimescale;
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$printtimescale();
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$printtimescale(t);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 0, "-my-ms", 8);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 1, "-my-ms", 10);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-6, 2, "-my-us", 12);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-9, 3, "-my-ns", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-12, 3, "-my-ps", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-15, 4, "-my-fs", 14);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 0, "-my-ms", 8);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-3, 1, "-my-ms", 10);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-6, 2, "-my-us", 12);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-9, 3, "-my-ns", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-12, 3, "-my-ps", 13);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$timeformat(-15, 4, "-my-fs", 14);
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$write("Time: '%t' 10ns=%0t\n", $time, t);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -4,28 +4,26 @@
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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module t (
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input clk
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);
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integer cyc = 0;
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integer cyc = 0;
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time texpect = `TEST_EXPECT;
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time texpect = `TEST_EXPECT;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$printtimescale;
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$write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect);
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if ($time != texpect) begin
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$write("[%0t] delta = %d\n", $time, $time - texpect);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$printtimescale;
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$write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect);
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if ($time != texpect) begin
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$write("[%0t] delta = %d\n", $time, $time - texpect);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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@ -4,22 +4,20 @@
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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module t (
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input clk
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);
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integer cyc = 0;
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integer cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$write("[%0t] In %m: Hi\n", $time);
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$printtimescale;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$write("[%0t] In %m: Hi\n", $time);
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$printtimescale;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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@ -4,24 +4,25 @@
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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timeunit 1ns;
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timeprecision 1ps;
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timeunit 1ns; timeprecision 1ps;
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initial begin
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`checkd($timeunit, -9);
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`checkd($timeunit(), -9);
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`checkd($timeunit(t), -9);
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initial begin
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`checkd($timeunit, -9);
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`checkd($timeunit(), -9);
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`checkd($timeunit(t), -9);
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`checkd($timeprecision, -12);
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`checkd($timeprecision(), -12);
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`checkd($timeprecision(t), -12);
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`checkd($timeprecision, -12);
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`checkd($timeprecision(), -12);
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`checkd($timeprecision(t), -12);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -8,46 +8,44 @@
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||||
import "DPI-C" function void dpii_check();
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
module t (
|
||||
input clk
|
||||
);
|
||||
|
||||
integer cyc = 0;
|
||||
// verilator lint_off REALCVT
|
||||
time digits = 5432109876.543210ns; // Will round to time units
|
||||
realtime rdigits = 5432109876.543210ns; // Will round to time precision
|
||||
time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double
|
||||
// verilator lint_on REALCVT
|
||||
integer cyc = 0;
|
||||
// verilator lint_off REALCVT
|
||||
time digits = 5432109876.543210ns; // Will round to time units
|
||||
realtime rdigits = 5432109876.543210ns; // Will round to time precision
|
||||
time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double
|
||||
// verilator lint_on REALCVT
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("- [%0t] tick\n", $time);
|
||||
$write("- [%0t] tick\n", $time);
|
||||
`endif
|
||||
if ($time >= 60) begin
|
||||
$write(":: In %m\n");
|
||||
$printtimescale;
|
||||
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
|
||||
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
|
||||
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
|
||||
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
|
||||
$timeformat(-9, 6, "ns", 16);
|
||||
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
|
||||
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
|
||||
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
|
||||
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
|
||||
$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
|
||||
$time, $stime, $stime, $stime);
|
||||
// verilator lint_off REALCVT
|
||||
$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
|
||||
$time, $realtime, $realtime, $realtime);
|
||||
// verilator lint_on REALCVT
|
||||
dpii_check();
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
if ($time >= 60) begin
|
||||
$write(":: In %m\n");
|
||||
$printtimescale;
|
||||
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
|
||||
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
|
||||
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
|
||||
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
|
||||
$timeformat(-9, 6, "ns", 16);
|
||||
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
|
||||
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
|
||||
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
|
||||
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
|
||||
$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
|
||||
$time, $stime, $stime, $stime);
|
||||
// verilator lint_off REALCVT
|
||||
$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
|
||||
$time, $realtime, $realtime, $realtime);
|
||||
// verilator lint_on REALCVT
|
||||
dpii_check();
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,10 +6,10 @@
|
|||
|
||||
// Intentionally no timescale here, nor in driver file
|
||||
module t;
|
||||
initial begin
|
||||
// Unspecified, but general consensus is 1s is default timeunit
|
||||
$printtimescale;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
initial begin
|
||||
// Unspecified, but general consensus is 1s is default timeunit
|
||||
$printtimescale;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
module pre_no_ts;
|
||||
endmodule
|
||||
|
||||
`timescale 1ns/1ns
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module t;
|
||||
pre_no_ts pre_no_ts();
|
||||
post_no_ts pst_no_ts();
|
||||
pre_no_ts pre_no_ts ();
|
||||
post_no_ts pst_no_ts ();
|
||||
endmodule
|
||||
|
||||
module post_no_ts;
|
||||
|
|
|
|||
|
|
@ -51,61 +51,61 @@ endmodule
|
|||
|
||||
|
||||
module r0;
|
||||
timeunit 10ns / 1ns;
|
||||
task check; $write("%m %0t\n", $time); endtask
|
||||
timeunit 10ns / 1ns;
|
||||
task check; $write("%m %0t\n", $time); endtask
|
||||
endmodule
|
||||
|
||||
module r1;
|
||||
timeunit 10ns;
|
||||
timeprecision 1ns;
|
||||
task check; $write("%m %0t\n", $time); endtask
|
||||
timeunit 10ns;
|
||||
timeprecision 1ns;
|
||||
task check; $write("%m %0t\n", $time); endtask
|
||||
endmodule
|
||||
|
||||
module t;
|
||||
sp2 sp2();
|
||||
sp1 sp1();
|
||||
sp0 sp0();
|
||||
sm1 sm1();
|
||||
sm2 sm2();
|
||||
sm3 sm3();
|
||||
sm4 sm4();
|
||||
sm5 sm5();
|
||||
sm6 sm6();
|
||||
sm7 sm7();
|
||||
sm8 sm8();
|
||||
sm9 sm9();
|
||||
sm10 sm10();
|
||||
sm11 sm11();
|
||||
sm12 sm12();
|
||||
sm13 sm13();
|
||||
sm14 sm14();
|
||||
sm15 sm15();
|
||||
sp2 sp2();
|
||||
sp1 sp1();
|
||||
sp0 sp0();
|
||||
sm1 sm1();
|
||||
sm2 sm2();
|
||||
sm3 sm3();
|
||||
sm4 sm4();
|
||||
sm5 sm5();
|
||||
sm6 sm6();
|
||||
sm7 sm7();
|
||||
sm8 sm8();
|
||||
sm9 sm9();
|
||||
sm10 sm10();
|
||||
sm11 sm11();
|
||||
sm12 sm12();
|
||||
sm13 sm13();
|
||||
sm14 sm14();
|
||||
sm15 sm15();
|
||||
|
||||
r0 r0();
|
||||
r1 r1();
|
||||
r0 r0();
|
||||
r1 r1();
|
||||
|
||||
final begin
|
||||
sp2.check();
|
||||
sp1.check();
|
||||
sp0.check();
|
||||
sm1.check();
|
||||
sm2.check();
|
||||
sm3.check();
|
||||
sm4.check();
|
||||
sm5.check();
|
||||
sm6.check();
|
||||
sm7.check();
|
||||
sm8.check();
|
||||
sm9.check();
|
||||
sm10.check();
|
||||
sm11.check();
|
||||
sm12.check();
|
||||
sm13.check();
|
||||
sm14.check();
|
||||
sm15.check();
|
||||
r0.check();
|
||||
r1.check();
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
final begin
|
||||
sp2.check();
|
||||
sp1.check();
|
||||
sp0.check();
|
||||
sm1.check();
|
||||
sm2.check();
|
||||
sm3.check();
|
||||
sm4.check();
|
||||
sm5.check();
|
||||
sm6.check();
|
||||
sm7.check();
|
||||
sm8.check();
|
||||
sm9.check();
|
||||
sm10.check();
|
||||
sm11.check();
|
||||
sm12.check();
|
||||
sm13.check();
|
||||
sm14.check();
|
||||
sm15.check();
|
||||
r0.check();
|
||||
r1.check();
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@
|
|||
%Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra'
|
||||
15 | `timescale 1ns / 1ps /extra
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
%Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value
|
||||
18 | timeunit 2ps;
|
||||
| ^~~
|
||||
%Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value
|
||||
19 | timeprecision 2ps;
|
||||
| ^~~
|
||||
%Error: t/t_timescale_parse_bad.v:18:12: timeunit illegal value
|
||||
18 | timeunit 2ps;
|
||||
| ^~~
|
||||
%Error: t/t_timescale_parse_bad.v:19:17: timeprecision illegal value
|
||||
19 | timeprecision 2ps;
|
||||
| ^~~
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -15,6 +15,6 @@
|
|||
`timescale 1ns / 1ps /extra
|
||||
|
||||
module t;
|
||||
timeunit 2ps; // Bad
|
||||
timeprecision 2ps; // Bad
|
||||
timeunit 2ps; // Bad
|
||||
timeprecision 2ps; // Bad
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,18 +6,18 @@
|
|||
|
||||
`timescale 1ns/1ns
|
||||
module t;
|
||||
p p ();
|
||||
p p ();
|
||||
|
||||
// Also check not-found modules
|
||||
localparam NOT = 0;
|
||||
if (NOT) begin
|
||||
NotFound not_found(.*);
|
||||
end
|
||||
// Also check not-found modules
|
||||
localparam NOT = 0;
|
||||
if (NOT) begin
|
||||
NotFound not_found(.*);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -34,10 +34,10 @@ input in;
|
|||
reg out;
|
||||
|
||||
table
|
||||
0 : 1;
|
||||
1 : 0;
|
||||
? : ?;
|
||||
x : x;
|
||||
0 : 1;
|
||||
1 : 0;
|
||||
? : ?;
|
||||
x : x;
|
||||
endtable
|
||||
endprimitive
|
||||
`endcelldefine
|
||||
|
|
|
|||
|
|
@ -4,27 +4,26 @@
|
|||
// any use, without warranty, 2021 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
timeunit 10ps;
|
||||
timeprecision 10ps;
|
||||
timeunit 10ps; timeprecision 10ps;
|
||||
|
||||
task show;
|
||||
$printtimescale;
|
||||
$printtimescale;
|
||||
endtask
|
||||
|
||||
module from_unit;
|
||||
task show;
|
||||
$printtimescale;
|
||||
endtask
|
||||
task show;
|
||||
$printtimescale;
|
||||
endtask
|
||||
endmodule
|
||||
|
||||
module t;
|
||||
from_unit from_unit();
|
||||
timeunit 100ps;
|
||||
initial begin
|
||||
show();
|
||||
from_unit.show();
|
||||
$printtimescale;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
from_unit from_unit ();
|
||||
timeunit 100ps;
|
||||
initial begin
|
||||
show();
|
||||
from_unit.show();
|
||||
$printtimescale;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue