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Fix --expand-limit not respected for expressions (#6670)

This commit is contained in:
Geza Lore 2025-11-10 17:18:33 +00:00 committed by GitHub
parent 0062a422a4
commit 8e35c81399
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GPG Key ID: B5690EEEBB952194
3 changed files with 24 additions and 2 deletions
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5
src/V3Expand.cpp
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@ -907,6 +907,8 @@ class ExpandVisitor final : public VNVisitor {
iterateChildren(nodep);
if (nodep->lhsp()->isWide()) {
if (isImpure(nodep)) return;
if (!doExpandWide(nodep->lhsp())) return;
if (!doExpandWide(nodep->rhsp())) return;
UINFO(8, " Wordize EQ/NEQ " << nodep);
// -> (0=={or{for each_word{WORDSEL(lhs,#)^WORDSEL(rhs,#)}}}
FileLine* const fl = nodep->fileline();
@ -933,6 +935,7 @@ class ExpandVisitor final : public VNVisitor {
FileLine* const fl = nodep->fileline();
if (nodep->lhsp()->isWide()) {
if (isImpure(nodep)) return;
if (!doExpandWide(nodep->lhsp())) return;
UINFO(8, " Wordize REDOR " << nodep);
// -> (0!={or{for each_word{WORDSEL(lhs,#)}}}
AstNodeExpr* newp = nullptr;
@ -957,6 +960,7 @@ class ExpandVisitor final : public VNVisitor {
FileLine* const fl = nodep->fileline();
if (nodep->lhsp()->isWide()) {
if (isImpure(nodep)) return;
if (!doExpandWide(nodep->lhsp())) return;
UINFO(8, " Wordize REDAND " << nodep);
// -> (0!={and{for each_word{WORDSEL(lhs,#)}}}
AstNodeExpr* newp = nullptr;
@ -988,6 +992,7 @@ class ExpandVisitor final : public VNVisitor {
iterateChildren(nodep);
if (nodep->lhsp()->isWide()) {
if (isImpure(nodep)) return;
if (!doExpandWide(nodep->lhsp())) return;
UINFO(8, " Wordize REDXOR " << nodep);
// -> (0!={redxor{for each_word{XOR(WORDSEL(lhs,#))}}}
FileLine* const fl = nodep->fileline();

2
test_regress/t/t_flag_expand_limit.py
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@ -13,6 +13,6 @@ test.scenarios('vlt')
test.compile(verilator_flags2=['--expand-limit 1 --stats -fno-dfg'])
test.file_grep(test.stats, r'Optimizations, expand limited\s+(\d+)', 3)
test.file_grep(test.stats, r'Optimizations, expand limited\s+(\d+)', 8)
test.passes()

19
test_regress/t/t_flag_expand_limit.v
View File

@ -14,7 +14,17 @@ module t #(parameter NV = 2000)
output [ 31:0] o,
input [319:0] bi,
output [319:0] bo
output [319:0] bo,
input [319:0] c_i1,
input [319:0] c_i2,
output c_eq_o,
output c_neq_o,
input [319:0] d_red_i,
output d_red_and_o,
output d_red_or_o,
output d_red_xor_o
);
// verilator lint_off WIDTH
@ -24,4 +34,11 @@ module t #(parameter NV = 2000)
assign bo = ~bi;
assign c_eq_o = c_i1 == c_i2;
assign c_neq_o = c_i1 != c_i2;
assign d_red_and_o = &d_red_i;
assign d_red_or_o = |d_red_i;
assign d_red_xor_o = ^d_red_i;
endmodule