Tests: t_fork_join_none_stmt (#5902 test)

test_regress/t/t_fork_join_none_stmt.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_fork_join_none_stmt.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+
+  bit stmt2 = '0;
+  bit proc1 = '0;
+
+  initial begin
+    $display("Statement 1");
+    fork
+      begin
+        // The join_none implies that here there's effectively a: #0;
+        $display("Process 1");
+        proc1 = '1;
+        `checkh(stmt2, 1'b1);
+      end
+    join_none
+    $display("Statement 2");
+    stmt2 = '1;
+    `checkh(proc1, 1'b0);
+
+    #1;
+    `checkh(proc1, 1'b1);
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule