Fix parameterized class function (#6659) (#6802)

src/V3Param.cpp

@@ -1313,11 +1313,20 @@ class ClassRefUnlinkerVisitor final : public VNVisitor {
 
 public:
     explicit ClassRefUnlinkerVisitor(AstNetlist* netlistp) { iterate(netlistp); }
-
     void visit(AstClassOrPackageRef* nodep) override {
         if (nodep->paramsp()) {
             if (AstClass* const classp = VN_CAST(nodep->classOrPackageSkipp(), Class)) {
-                if (!classp->user3p()) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+                if (!classp->user3p()) {
+                    // Check if this ClassOrPackageRef is the lhsp of a DOT node
+                    AstDot* const dotp = VN_CAST(nodep->backp(), Dot);
+                    if (dotp && dotp->lhsp() == nodep) {
+                        // Replace DOT with just its rhsp to avoid leaving DOT with null lhsp
+                        dotp->replaceWith(dotp->rhsp()->unlinkFrBack());
+                        VL_DO_DANGLING2(pushDeletep(dotp), dotp, nodep);
+                    } else {
+                        VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+                    }
+                }
             }
         }
     }

test_regress/t/t_class_param_typedef3.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_class_param_typedef3.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+class func_c #(parameter p_width=4);
+   static function logic[p_width-1:0] func(
+      input logic[p_width-1:0] inb
+   );
+      func = inb;
+   endfunction
+endclass
+
+module modA #(parameter p_width = 7)(
+   input logic [p_width-1:0] sig_a
+   ,output logic [p_width-1:0] sig_b
+);
+   assign sig_b = func_c#(p_width)::func(sig_a);
+endmodule
+
+module the_top();
+   localparam int Size = 3;
+
+   logic [Size-1:0] sig_a;
+   logic [Size-1:0] sig_b;
+
+   modA #(.p_width(Size)) modA(
+      .sig_a(sig_a)
+      ,.sig_b(sig_b)
+   );
+
+   //assign sig_b = func_c#(p_width)::func(inb_i);
+
+   initial begin
+      sig_a = 'h3;
+      #1;
+      $display("sig_a=%d, sig_b=%d", sig_a, sig_b);
+      if(sig_b != 'h3) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_class_param_typedef4.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_class_param_typedef4.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+class func_c #(parameter p_width=4);
+  static function logic[p_width-1:0] func(
+    input logic[p_width-1:0] inb
+  );
+    func = inb;
+  endfunction
+endclass
+
+module modA #(parameter p_width = 7)(
+  input logic [p_width-1:0] sig_a
+  ,output logic [p_width-1:0] sig_b
+);
+  assign sig_b = func_c#(p_width)::func(sig_a);
+endmodule
+
+module the_top();
+  localparam int Size = 3;
+
+  logic [Size-1:0] sig_a;
+  logic [Size-1:0] sig_b;
+  logic [Size-1:0] sig_c;
+
+  modA #(.p_width(Size)) modA(
+    .sig_a(sig_a)
+    ,.sig_b(sig_b)
+  );
+
+  initial begin
+    sig_a = 'h3;
+    sig_c = func_c#(Size)::func('h5);
+    #1;
+    if(sig_b != 'h3) $stop;
+    if(sig_c != 'h5) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule