parent
081ecbd095
commit
a8f62703ab
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@ -197,6 +197,7 @@ Nathan Graybeal
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Nathan Kohagen
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Nathan Myers
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Nick Brereton
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Nikolay Puzanov
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Nolan Poe
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Oleh Maksymenko
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Patrick Stewart
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@ -3406,7 +3406,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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if (!baseFuncp || !baseFuncp->pureVirtual()) continue;
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const bool existsInDerived = foundp && !foundp->imported();
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if (m_statep->forPrimary() && !existsInDerived
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&& !derivedClassp->isInterfaceClass()) {
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&& !derivedClassp->isInterfaceClass() && !derivedClassp->isVirtual()) {
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derivedClassp->v3error(
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"Class " << derivedClassp->prettyNameQ() << impOrExtends
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<< baseClassp->prettyNameQ()
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint()
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test.passes()
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@ -0,0 +1,23 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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virtual class Base;
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pure virtual function void f0();
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endclass
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virtual class Child extends Base;
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pure virtual function void f1();
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endclass
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class Impl extends Child;
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virtual function void f0();
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endfunction
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virtual function void f1();
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endfunction
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endclass
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module t;
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endmodule
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