Fix accessing non-rand struct member in constraints (#6960)

src/V3Randomize.cpp

@@ -1121,6 +1121,7 @@ class ConstraintExprVisitor final : public VNVisitor {
         editSMT(nodep, nodep->fromp(), lsbp, msbp);
     }
     void visit(AstStructSel* nodep) override {
+        if (editFormat(nodep)) return;
         m_structSel = true;
         if (VN_IS(nodep->fromp()->dtypep()->skipRefp(), StructDType)) {
             AstNodeExpr* const fromp = nodep->fromp();
@@ -1154,7 +1155,6 @@ class ConstraintExprVisitor final : public VNVisitor {
             }
         }
         iterateChildren(nodep);
-        if (editFormat(nodep)) return;
         FileLine* const fl = nodep->fileline();
         AstSFormatF* newp = nullptr;
         if (VN_AS(nodep->fromp(), SFormatF)->name() == "%@.%@") {

test_regress/t/t_randomize_struct_sel.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_randomize_struct_sel.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct {int x;} struct_t;
+
+class ConstrClass;
+  struct_t obj;
+  rand int rand_int;
+  constraint addr_c {rand_int == obj.x;}
+endclass
+
+module t;
+  ConstrClass o;
+  initial begin
+    o = new;
+    o.obj.x = 42;
+    if (o.randomize() == 0) begin
+      $display("Randomization failed");
+      $stop;
+    end else if (o.obj.x != o.rand_int) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule