Fix segfault in V3Slice (#6899)

src/V3Slice.cpp

@@ -125,6 +125,7 @@ class SliceVisitor final : public VNVisitor {
                     nodep->v3error("Array initialization has too few elements, need element "
                                    << elemIdx);
                     m_assignError = true;
+                    break;
                 }
                 const AstNodeDType* itemRawDTypep = itemp->dtypep()->skipRefp();
                 const VCastable castable

test_regress/t/t_init_array_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_init_array_bad.v:8:35: Array initialization has too few elements, need element 2
+    8 |     bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
+      |                                   ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_init_array_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.lint(fails=True, v_flags2=['-Wno-WIDTHTRUNC'], expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_init_array_bad.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+    bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
+    initial $finish;
+endmodule