Fix time to not advance after `$finish` (#7095).

Fixes #7095.

Changes

@@ -113,6 +113,7 @@ Verilator 5.045 devel
 * Fix inside operator crash with impure expression and unsized range literals (#7063) (#7067). [Yilou Wang]
 * Fix constant propagating DPI-written variables (#7074). [Geza Lore, Testorrent USA, Inc.]
 * Fix conditional expressions in constraints (#7087). [Ryszard Rozak, Antmicro Ltd.]
+* Fix time to not advance after `$finish` (#7095).
 
 
 Verilator 5.044 2026-01-01

src/V3EmitCModel.cpp

@@ -458,7 +458,7 @@ class EmitCModel final : public EmitCFunc {
             putns(modp, "bool " + EmitCUtil::topClassName()
                             + "::eventsPending() { return !vlSymsp->TOP.");
             puts(delaySchedp->nameProtect());
-            puts(".empty(); }\n\n");
+            puts(".empty() && !contextp()->gotFinish(); }\n\n");
 
             putns(modp, "uint64_t " + EmitCUtil::topClassName()
                             + "::nextTimeSlot() { return vlSymsp->TOP.");

test_regress/t/t_timing_finish3.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.file_grep_not(test.run_log_filename, r'%Error:')  # As $finish will suppress $stop
+
+test.passes()

test_regress/t/t_timing_finish3.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+  task phase();
+    #1000;
+    $display("ended");
+  endtask
+
+  initial begin
+    fork
+      phase();
+    join_none
+    #123;
+    $display("[%0t] $finish", $time);
+    $finish;
+  end
+
+  final begin
+    $display("[%0t] final", $time);
+    `checkd($time, 123);
+  end
+
+endmodule

test_regress/t/t_timing_timescale.out

@@ -22,5 +22,5 @@
 [1e-05] clkb is 1
 [1e-05] Finishing (t.bot)
 *-* All Finished *-*
-[10500] final (t)
-[1.05e-05] final (t.bot) count was 21
+[10000] final (t)
+[1e-05] final (t.bot) count was 21