Support `#1step` delay as statement (#6671)

src/V3Timing.cpp

@@ -891,6 +891,10 @@ class TimingControlVisitor final : public VNVisitor {
                                     new AstConst{flp, AstConst::Unsized64{},
                                                  static_cast<uint64_t>(timescaleFactor)}};
             }
+        } else if (constp->num().is1Step()) {
+            VL_DO_DANGLING(valuep->deleteTree(), valuep);
+            valuep = new AstConst{flp, AstConst::Unsized64{}, 1};
+            valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
         }
         // Replace self with a 'co_await dlySched.delay(<valuep>)'
         AstCMethodHard* const delayMethodp = new AstCMethodHard{

src/verilog.y

@@ -2949,6 +2949,7 @@ delay_value<nodeExprp>:         // ==IEEE:delay_value
         |       yaINTNUM                                { $$ = new AstConst{$<fl>1, *$1}; }
         |       yaFLOATNUM                              { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
         |       timeNumAdjusted                         { $$ = $1; }
+        |       y1STEP                                  { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
         ;
 
 delayExpr<nodeExprp>:
@@ -6165,7 +6166,6 @@ clocking_skewE<nodeExprp>:          // IEEE: [clocking_skew]
 
 clocking_skew<nodeExprp>:           // IEEE: clocking_skew
                 delay_control                           { $$ = $1->lhsp()->unlinkFrBack(); $1->deleteTree(); }
-        |      '#' y1STEP                               { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
         |      yPOSEDGE delay_controlE                  { $$ = nullptr;
                                                           BBUNSUP($1, "Unsupported: clocking event edge override"); DEL($2); }
         |      yNEGEDGE delay_controlE                  { $$ = nullptr;

test_regress/t/t_clocking_bad2.out

@@ -1,6 +1,6 @@
-%Error: t/t_clocking_bad2.v:15:32: 1step not allowed as output skew
+%Error: t/t_clocking_bad2.v:15:33: 1step not allowed as output skew
    15 |        default input #1 output #1step;
-      |                                ^
+      |                                 ^~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: t/t_clocking_bad2.v:16:23: Multiple default input skews not allowed
    16 |        default input #2 output #2;
@@ -8,9 +8,9 @@
 %Error: t/t_clocking_bad2.v:16:33: Multiple default output skews not allowed
    16 |        default input #2 output #2;
       |                                 ^
-%Error: t/t_clocking_bad2.v:17:15: 1step not allowed as output skew
+%Error: t/t_clocking_bad2.v:17:16: 1step not allowed as output skew
    17 |        output #1step out;
-      |               ^
+      |                ^~~~~
 %Error: t/t_clocking_bad2.v:18:8: Multiple clockvars with the same name not allowed
    18 |        output out;
       |        ^~~~~~

test_regress/t/t_delay_1step.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_delay_1step.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  timeunit 10s;
+  timeprecision 1s;
+
+  initial begin
+    #1;
+    if ($time != 1) $stop;
+    repeat(10) #1step;
+    if ($time != 2) $stop;
+    #10;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule