Optimize continuous assignments with function on RHS in Dfg (#7096)

src/V3DfgAstToDfg.cpp

@@ -205,7 +205,11 @@ class AstToDfgVisitor final : public VNVisitor {
 
         // Can only handle combinational logic
         if (nodep->sentreep()) return false;
-        if (kwd != VAlwaysKwd::ALWAYS && kwd != VAlwaysKwd::ALWAYS_COMB) return false;
+        if (kwd != VAlwaysKwd::ALWAYS  //
+            && kwd != VAlwaysKwd::ALWAYS_COMB  //
+            && kwd != VAlwaysKwd::CONT_ASSIGN) {
+            return false;
+        }
 
         // Potentially convertible block
         ++m_ctx.m_inputs;

src/V3DfgSynthesize.cpp

@@ -469,7 +469,8 @@ public:
     // Convert AstAssign to Dfg, return true if successful.
     // Fills 'updates' with bindings for assigned variables.
     bool convert(std::vector<std::pair<Variable*, DfgVertexVar*>>& updates, DfgLogic& vtx,
-                 AstAssign* nodep) {
+                 AstNodeAssign* nodep) {
+        UASSERT_OBJ(VN_IS(nodep, Assign) || VN_IS(nodep, AssignW), nodep, "Bad NodeAssign");
         UASSERT_OBJ(updates.empty(), nodep, "'updates' should be empty");
         VL_RESTORER(m_updatesp);
         VL_RESTORER(m_logicp);
@@ -1315,7 +1316,8 @@ class AstToDfgSynthesize final {
         std::vector<std::pair<Variable*, DfgVertexVar*>> updates;
         for (AstNodeStmt* const stmtp : stmtps) {
             // Regular statements
-            if (AstAssign* const ap = VN_CAST(stmtp, Assign)) {
+            AstNodeAssign* const ap = VN_CAST(stmtp, NodeAssign);
+            if (ap && (VN_IS(ap, Assign) || VN_IS(ap, AssignW))) {
                 // Convert this assignment
                 if (!m_converter.convert(updates, *m_logicp, ap)) {
                     ++m_ctx.m_synt.nonSynConv;

test_regress/t/t_dfg_synthesis.py

@@ -34,6 +34,8 @@ with open(rdFile, 'r', encoding="utf8") as rdFh, \
             nAlwaysReverted += 1
         elif re.search(r'^\s*always', line):
             nAlwaysSynthesized += 1
+        elif re.search(r'^\s*wire.*=', line):
+            nAlwaysSynthesized += 1
         line = line.split("//")[0]
         m = re.search(r'`signal\((\w+),', line)
         if not m:

test_regress/t/t_dfg_synthesis.v

@@ -10,6 +10,28 @@ package pkg;
   function automatic logic [7:0] sub(input logic [7:0] a, input logic [7:0] b);
     return a - b;
   endfunction
+
+  function automatic logic [7:0] branchy(input logic [7:0] a, input logic [7:0] b);
+    if (a[0]) begin
+      return b + 8'd1;
+    end else if (a[1]) begin
+      return b + 8'd2;
+    end else if (a[2]) begin
+      return b + 8'd3;
+    end else if (a[3]) begin
+      return b + 8'd4;
+    end else if (a[4]) begin
+      return b + 8'd5;
+    end else if (a[5]) begin
+      return b + 8'd6;
+    end else if (a[6]) begin
+      return b + 8'd7;
+    end else if (a[7]) begin
+      return b + 8'd8;
+    end else begin
+      return b;
+    end
+  endfunction
 endpackage
 
 module t (
@@ -545,4 +567,7 @@ module t (
   end
   `signal(FUNC_2, func_2);
 
+  wire logic [7:0] func_3 = pkg::branchy(rand_a[7:0], rand_b[7:0]);
+  `signal(FUNC_3, func_3);
+
 endmodule

test_regress/t/t_func_crc.py

@@ -18,6 +18,6 @@ test.compile(
 test.execute()
 
 if test.vlt:
-    test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 3888)
+    test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 3416)
 
 test.passes()