Fix type assignments for arrays of parameter types (#6955)

src/V3LinkDot.cpp

@@ -4049,8 +4049,12 @@ class LinkDotResolveVisitor final : public VNVisitor {
                         [this](AstVar* v, AstRefDType* r) { return promoteVarToParamType(v, r); },
                         [this]() { return indent(); });
 
-                    replaceWithCheckBreak(nodep, refp);
-                    VL_DO_DANGLING(pushDeletep(nodep), nodep);
+                    if (VN_IS(nodep->backp(), SelExtract)) {
+                        m_packedArrayDtp = refp;
+                    } else {
+                        replaceWithCheckBreak(nodep, refp);
+                        VL_DO_DANGLING(pushDeletep(nodep), nodep);
+                    }
                 }
             }
             if (!ok) {

test_regress/t/t_lparam_assign_iface_typedef2.v

@@ -18,6 +18,7 @@ module top ();
   localparam type p0_t = if0.rq_t;
 
   initial begin
+    if ($bits(p0_t) != 8) $stop;
     #1;
     $write("*-* All Finished *-*\n");
     $finish;

test_regress/t/t_lparam_assign_iface_typedef4.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_lparam_assign_iface_typedef4.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+//
+
+interface x_if #(
+    parameter int a_width = 3
+) ();
+
+  typedef struct packed {logic [a_width-1:0] addr;} rq_t;
+endinterface
+
+module top ();
+  x_if #(.a_width(8)) if0 ();
+
+  localparam type p0_t = if0.rq_t [1:0];
+
+  initial begin
+    if ($bits(p0_t) != 16) $stop;
+    #1;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule

test_regress/t/t_param_type_chain.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2026 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_param_type_chain.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+  // Inputs
+  clk
+  );
+  input clk;
+
+  sub sub_default();
+  sub #(.foo_t (logic[7:0])) sub_8();
+
+  always @ (posedge clk) begin
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule
+
+module sub #(
+  parameter type foo_t = logic,
+  parameter type bar_t = foo_t[1:0]
+);
+  initial begin
+    $display("%m foo_t = %0d bar_t = %0d", $bits(foo_t), $bits(bar_t));
+    if (2 * $bits(foo_t) != $bits(bar_t)) $stop;
+  end
+endmodule