Fix clocking unsupported tristate assign error (#6942).

Fixes #6942.

src/V3Tristate.cpp

@@ -316,17 +316,16 @@ public:
         const TristateVertex* const vertexp = reinterpret_cast<TristateVertex*>(nodep->user4p());
         return vertexp && vertexp->feedsTri();
     }
-    void didProcess(AstNode* nodep) {
-        TristateVertex* const vertexp = reinterpret_cast<TristateVertex*>(nodep->user4p());
-        if (!vertexp) {
+    void didProcess(AstNode* nodep, bool quiet = false) {
+        if (TristateVertex* const vertexp = reinterpret_cast<TristateVertex*>(nodep->user4p())) {
+            // We don't warn if no vertexp->isTristate() as the creation
+            // process makes midling nodes that don't have it set
+            vertexp->processed(true);
+        } else if (!quiet) {
             // Not v3errorSrc as no reason to stop the world
             nodep->v3warn(E_UNSUPPORTED,
                           "Unsupported tristate construct (not in propagation graph): "
                               << nodep->prettyTypeName());
-        } else {
-            // We don't warn if no vertexp->isTristate() as the creation
-            // process makes midling nodes that don't have it set
-            vertexp->processed(true);
         }
     }
     // ITERATOR METHODS
@@ -1340,6 +1339,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                 nodep->rhsp()->user1p(nullptr);
                 UINFO(9, "   enp<-rhs " << nodep->lhsp()->user1p());
                 m_tgraph.didProcess(nodep);
+            } else {
+                m_tgraph.didProcess(nodep, true);
             }
             m_alhs = true;  // And user1p() will indicate tristate equation, if any
             if (AstAssignW* const assignWp = VN_CAST(nodep, AssignW)) {

test_regress/t/t_tri_clocking.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_tri_clocking.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface wb_ifc;
+  logic clk;
+  wire rst;
+  tri0 cyc;
+  clocking mck @(posedge clk);
+    input rst;
+    output cyc;
+  endclocking
+endinterface
+
+module t;
+  wb_ifc wb_ma ();
+  initial $finish;
+endmodule