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@ -4663,7 +4663,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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}
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if (nodep->name() == "local::") {
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if (!m_randSymp) {
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if (!m_randSymp && !m_randMethodCallp) {
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nodep->v3error("Illegal 'local::' outside 'randomize() with'"
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" (IEEE 1800-2023 18.7.1)");
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m_ds.m_dotErr = true;
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,61 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class item_cls #(type T = int);
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rand T value;
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endclass
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class multi_param_cls #(type T = int, int WIDTH = 8);
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rand T data;
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rand bit [WIDTH-1:0] mask;
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endclass
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class driver_cls #(type T = int);
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function int do_rand(T val);
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item_cls#(T) itemp;
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itemp = new();
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void'(itemp.randomize() with { value == local::val; });
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return (itemp.value == val) ? 32'd1 : 32'd0;
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endfunction
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endclass
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class multi_driver_cls #(type T = int, int WIDTH = 8);
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function int do_rand(T val, bit [WIDTH-1:0] m);
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multi_param_cls#(T, WIDTH) itemp;
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itemp = new();
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void'(itemp.randomize() with {
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data == local::val;
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mask == local::m;
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});
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return (itemp.data == val && itemp.mask == m) ? 32'd1 : 32'd0;
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endfunction
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endclass
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module t;
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initial begin
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driver_cls#(int) drvp;
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multi_driver_cls#(int, 8) mdrvp;
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drvp = new();
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mdrvp = new();
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repeat (20) begin
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`checkd(drvp.do_rand(32'd42), 32'd1)
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end
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repeat (20) begin
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`checkd(mdrvp.do_rand(32'd99, 8'hAB), 32'd1)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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