Internals: Add `--fourstate` flag and FUTURE warning (#7279)
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@ -856,6 +856,11 @@ List Of Warnings
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pass.
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.. option:: FUTURE
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Warns that a feature is under development and not yet supported.
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.. option:: GENCLK
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Historical, never issued since version 5.000.
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@ -107,6 +107,7 @@ public:
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ENUMVALUE, // Error: enum type needs explicit cast
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EOFNEWLINE, // End-of-file missing newline
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FUNCTIMECTL, // Functions cannot have timing/delay/wait
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FUTURE, // Feature is under development and not yet supported
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GENCLK, // Generated Clock. Historical, never issued.
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GENUNNAMED, // Generate unnamed, without label
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HIERBLOCK, // Ignored hierarchical block setting
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@ -223,7 +224,7 @@ public:
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"CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", "CONSTRAINTIGN",
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"CONTASSREG", "COVERIGN", "DECLFILENAME", "DEFOVERRIDE", "DEFPARAM", "DEPRECATED",
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"ENCAPSULATED", "ENDLABEL", "ENUMITEMWIDTH", "ENUMVALUE", "EOFNEWLINE", "FUNCTIMECTL",
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"GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", "IFDEPTH", "IGNOREDRETURN",
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"FUTURE", "GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", "IFDEPTH", "IGNOREDRETURN",
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"IMPERFECTSCH", "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH",
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"INFINITELOOP", "INITIALDLY", "INSECURE", "INSIDETRUE", "LATCH", "LITENDIAN",
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"MINTYPMAXDLY", "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP",
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@ -1056,6 +1056,10 @@ void V3Options::notify() VL_MT_DISABLED {
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"--main not usable with SystemC. Suggest see examples for sc_main().");
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}
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if (fourstate()) {
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cmdfl->v3warn(FUTURE, "--fourstate is not supported as is under development");
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}
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if (coverage() && savable()) {
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cmdfl->v3error("Unsupported: --coverage and --savable not supported together");
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}
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@ -1436,6 +1440,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
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parseOptsFile(fl, parseFileArg(optdir, valp), false);
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}).notForRerun();
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DECL_OPTION("-flatten", OnOff, &m_flatten);
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DECL_OPTION("-fourstate", OnOff, &m_fourstate).undocumented();
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DECL_OPTION("-future0", CbVal, [this](const char* valp) { addFuture0(valp); });
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DECL_OPTION("-future1", CbVal, [this](const char* valp) { addFuture1(valp); });
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@ -254,6 +254,7 @@ private:
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bool m_emitAccessors = false; // main switch: --emit-accessors
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bool m_exe = false; // main switch: --exe
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bool m_flatten = false; // main switch: --flatten
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bool m_fourstate = false; // main switch: --fourstate
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bool m_hierarchical = false; // main switch: --hierarchical
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bool m_ignc = false; // main switch: --ignc
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bool m_jsonOnly = false; // main switch: --json-only
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@ -545,6 +546,7 @@ public:
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bool emitAccessors() const { return m_emitAccessors; }
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bool exe() const { return m_exe; }
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bool flatten() const { return m_flatten; }
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bool fourstate() const { return m_fourstate; }
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bool gmake() const { return m_gmake; }
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bool makeJson() const { return m_makeJson; }
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bool threadsDpiPure() const { return m_threadsDpiPure; }
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@ -0,0 +1,4 @@
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%Warning-FUTURE: --fourstate is not supported as is under development
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... For warning description see https://verilator.org/warn/FUTURE?v=latest
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... Use "/* verilator lint_off FUTURE */" and lint_on around source to disable this message.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.lint(verilator_flags2=['--fourstate'], fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,21 @@
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// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
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//
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// Assignment compatibility test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic a = 'z;
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logic b;
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assign b = ~a;
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initial begin
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#1;
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if (b !== 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary', '--no-fourstate'])
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test.execute()
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test.passes()
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@ -0,0 +1,21 @@
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// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
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//
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// Assignment compatibility test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic a = 'z;
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logic b;
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assign b = ~a;
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initial begin
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#1;
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if (b !== 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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