Internals: Add `--fourstate` flag and FUTURE warning (#7279)

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Igor Zaworski 2026-03-18 18:45:36 +01:00 committed by GitHub
parent a2154e9119
commit 907e775aa6
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9 changed files with 94 additions and 1 deletions

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@ -856,6 +856,11 @@ List Of Warnings
pass.
.. option:: FUTURE
Warns that a feature is under development and not yet supported.
.. option:: GENCLK
Historical, never issued since version 5.000.

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@ -107,6 +107,7 @@ public:
ENUMVALUE, // Error: enum type needs explicit cast
EOFNEWLINE, // End-of-file missing newline
FUNCTIMECTL, // Functions cannot have timing/delay/wait
FUTURE, // Feature is under development and not yet supported
GENCLK, // Generated Clock. Historical, never issued.
GENUNNAMED, // Generate unnamed, without label
HIERBLOCK, // Ignored hierarchical block setting
@ -223,7 +224,7 @@ public:
"CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", "CONSTRAINTIGN",
"CONTASSREG", "COVERIGN", "DECLFILENAME", "DEFOVERRIDE", "DEFPARAM", "DEPRECATED",
"ENCAPSULATED", "ENDLABEL", "ENUMITEMWIDTH", "ENUMVALUE", "EOFNEWLINE", "FUNCTIMECTL",
"GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", "IFDEPTH", "IGNOREDRETURN",
"FUTURE", "GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", "IFDEPTH", "IGNOREDRETURN",
"IMPERFECTSCH", "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH",
"INFINITELOOP", "INITIALDLY", "INSECURE", "INSIDETRUE", "LATCH", "LITENDIAN",
"MINTYPMAXDLY", "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP",

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@ -1056,6 +1056,10 @@ void V3Options::notify() VL_MT_DISABLED {
"--main not usable with SystemC. Suggest see examples for sc_main().");
}
if (fourstate()) {
cmdfl->v3warn(FUTURE, "--fourstate is not supported as is under development");
}
if (coverage() && savable()) {
cmdfl->v3error("Unsupported: --coverage and --savable not supported together");
}
@ -1436,6 +1440,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
parseOptsFile(fl, parseFileArg(optdir, valp), false);
}).notForRerun();
DECL_OPTION("-flatten", OnOff, &m_flatten);
DECL_OPTION("-fourstate", OnOff, &m_fourstate).undocumented();
DECL_OPTION("-future0", CbVal, [this](const char* valp) { addFuture0(valp); });
DECL_OPTION("-future1", CbVal, [this](const char* valp) { addFuture1(valp); });

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@ -254,6 +254,7 @@ private:
bool m_emitAccessors = false; // main switch: --emit-accessors
bool m_exe = false; // main switch: --exe
bool m_flatten = false; // main switch: --flatten
bool m_fourstate = false; // main switch: --fourstate
bool m_hierarchical = false; // main switch: --hierarchical
bool m_ignc = false; // main switch: --ignc
bool m_jsonOnly = false; // main switch: --json-only
@ -545,6 +546,7 @@ public:
bool emitAccessors() const { return m_emitAccessors; }
bool exe() const { return m_exe; }
bool flatten() const { return m_flatten; }
bool fourstate() const { return m_fourstate; }
bool gmake() const { return m_gmake; }
bool makeJson() const { return m_makeJson; }
bool threadsDpiPure() const { return m_threadsDpiPure; }

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@ -0,0 +1,4 @@
%Warning-FUTURE: --fourstate is not supported as is under development
... For warning description see https://verilator.org/warn/FUTURE?v=latest
... Use "/* verilator lint_off FUTURE */" and lint_on around source to disable this message.
%Error: Exiting due to

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.lint(verilator_flags2=['--fourstate'], fails=True, expect_filename=test.golden_filename)
test.passes()

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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
//
// Assignment compatibility test.
//
// This file ONLY is placed under the Creative Commons Public Domain
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t;
logic a = 'z;
logic b;
assign b = ~a;
initial begin
#1;
if (b !== 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--binary', '--no-fourstate'])
test.execute()
test.passes()

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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
//
// Assignment compatibility test.
//
// This file ONLY is placed under the Creative Commons Public Domain
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t;
logic a = 'z;
logic b;
assign b = ~a;
initial begin
#1;
if (b !== 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule