Fix library/hier_block tracing when top name is empty (#7200)

src/V3TraceDecl.cpp

@@ -322,9 +322,14 @@ class TraceDeclVisitor final : public VNVisitor {
 
         // Call the initialization function for the library instance
         AstCStmt* const initp = new AstCStmt{flp};
-        initp->add("tracep->initLib(vlSymsp->name() + ");
-        initp->add(new AstConst{flp, AstConst::String{}, "." + AstNode::prettyName(path)});
-        initp->add(");\n");
+        initp->add("{\n");
+        initp->add("std::string __VlibName = vlSymsp->name();\n");
+        initp->add("if (!__VlibName.empty()) __VlibName += '.';\n");
+        initp->add("__VlibName += ");
+        initp->add(new AstConst{flp, AstConst::String{}, AstNode::prettyName(path)});
+        initp->add(";\n");
+        initp->add("tracep->initLib(__VlibName);\n");
+        initp->add("}\n");
 
         placeholderp->addNextHere(initp);
         // Delete the placeholder

test_regress/driver.py

@@ -1191,6 +1191,7 @@ class VlTest:
             'make_flags': [],
             'tee': True,
             'timing_loop': False,
+            'main_top_name': "top",
         }
         param.update(vars(self))
         param.update(kwargs)
@@ -1360,7 +1361,7 @@ class VlTest:
                 return
 
             if not param['fails'] and param['make_main']:
-                self._make_main(param['timing_loop'])
+                self._make_main(param['timing_loop'], param['main_top_name'])
 
             if (param['verilator_make_gmake']
                     or (not param['verilator_make_gmake'] and not param['verilator_make_cmake'])):
@@ -2011,7 +2012,7 @@ class VlTest:
                     return size + line
         return size + firstline
 
-    def _make_main(self, timing_loop: bool) -> None:
+    def _make_main(self, timing_loop: bool, main_top_name: str) -> None:
         if timing_loop and self.sc:
             self.error("Cannot use timing loop and SystemC together!")
 
@@ -2108,7 +2109,7 @@ class VlTest:
             fh.write("    srand48(5);\n")  # Ensure determinism
             if self.verilated_randReset is not None and self.verilated_randReset != "":
                 fh.write("    contextp->randReset(" + str(self.verilated_randReset) + ");\n")
-            fh.write("    topp.reset(new " + self.vm_prefix + "{\"top\"});\n")
+            fh.write("    topp.reset(new " + self.vm_prefix + '{"' + main_top_name + '"});\n')
             if self.verilated_debug:
                 fh.write("    contextp->internalsDump()\n;")
 

test_regress/t/t_hier_block_trace_fst.py

@@ -10,7 +10,8 @@
 import vltest_bootstrap
 
 noinline = "noinl" in test.name
-if not noinline:
+notop = "notop" in test.name
+if not noinline and not notop:
     test.priority(30)
 test.scenarios('vlt_all')
 test.top_filename = "t/t_hier_block.v"
@@ -30,16 +31,19 @@ verilator_common_flags = [
 verilator_hier_flags = verilator_common_flags + ['--hierarchical']
 if noinline:
     verilator_hier_flags.extend(["+define+NO_INLINE"])
+main_top_name = "top"
+if notop:
+    main_top_name = ""
 
 # Compile hierarchically
 test.vm_prefix = "Vhier"
 test.main_filename = test.obj_dir + "/Vhier__main.cpp"
-test.compile(verilator_flags2=verilator_hier_flags)
+test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
 
 # Compile non hierarchically
 test.vm_prefix = "Vnonh"
 test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
-test.compile(verilator_flags2=verilator_common_flags)
+test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
 
 trace_hier = test.trace_filename.replace("simx", "hier")
 trace_nonh = test.trace_filename.replace("simx", "nonh")

test_regress/t/t_hier_block_trace_fst_notop.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+import runpy
+
+test.priority(30)
+test.scenarios('vlt_all')
+
+runpy.run_path("t/t_hier_block_trace_fst.py", globals())

test_regress/t/t_hier_block_trace_saif.py

@@ -10,11 +10,11 @@
 import vltest_bootstrap
 
 noinline = "noinl" in test.name
-if not noinline:
+notop = "notop" in test.name
+if not noinline and not notop:
     test.priority(30)
 test.scenarios('vlt_all')
 test.top_filename = "t/t_hier_block.v"
-test.golden_filename = "t/t_hier_block_trace_saif.out"
 
 verilator_common_flags = [
     't/t_hier_block.cpp',
@@ -31,16 +31,19 @@ verilator_common_flags = [
 verilator_hier_flags = verilator_common_flags + ['--hierarchical']
 if noinline:
     verilator_hier_flags.extend(["+define+NO_INLINE"])
+main_top_name = "top"
+if notop:
+    main_top_name = ""
 
 # Compile hierarchically
 test.vm_prefix = "Vhier"
 test.main_filename = test.obj_dir + "/Vhier__main.cpp"
-test.compile(verilator_flags2=verilator_hier_flags)
+test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
 
 # Compile non hierarchically
 test.vm_prefix = "Vnonh"
 test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
-test.compile(verilator_flags2=verilator_common_flags)
+test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
 
 trace_hier = test.trace_filename.replace("simx", "hier")
 trace_nonh = test.trace_filename.replace("simx", "nonh")

test_regress/t/t_hier_block_trace_saif_notop.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+import runpy
+
+test.priority(30)
+test.scenarios('vlt_all')
+
+runpy.run_path("t/t_hier_block_trace_saif.py", globals())

test_regress/t/t_hier_block_trace_vcd.py

@@ -12,7 +12,8 @@ import vltest_bootstrap
 import re
 
 noinline = "noinl" in test.name
-if not noinline:
+notop = "notop" in test.name
+if not noinline and not notop:
     test.priority(30)
 test.scenarios('vlt_all')
 test.top_filename = "t/t_hier_block.v"
@@ -32,16 +33,19 @@ verilator_common_flags = [
 verilator_hier_flags = verilator_common_flags + ['--hierarchical']
 if noinline:
     verilator_hier_flags.extend(["+define+NO_INLINE"])
+main_top_name = "top"
+if notop:
+    main_top_name = ""
 
 # Compile hierarchically
 test.vm_prefix = "Vhier"
 test.main_filename = test.obj_dir + "/Vhier__main.cpp"
-test.compile(verilator_flags2=verilator_hier_flags)
+test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name)
 
 # Compile non hierarchically
 test.vm_prefix = "Vnonh"
 test.main_filename = test.obj_dir + "/Vnonh__main.cpp"
-test.compile(verilator_flags2=verilator_common_flags)
+test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name)
 
 trace_hier = test.trace_filename.replace("simx", "hier")
 trace_nonh = test.trace_filename.replace("simx", "nonh")

test_regress/t/t_hier_block_trace_vcd_notop.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+import runpy
+
+test.priority(30)
+test.scenarios('vlt_all')
+
+runpy.run_path("t/t_hier_block_trace_vcd.py", globals())