Fix randomize of real (#7115).

Fixes #7115.

Changes

@@ -121,6 +121,7 @@ Verilator 5.045 devel
 * Fix time to not advance after `$finish` (#7095).
 * Fix associative array size() constraint generating invalid resize() call (#7103) (#7112). [Yilou Wang]
 * Fix circular class reference %p-printing causing infinite recursion (#7106).
+* Fix randomize of real (#7115). [Srinivasan Venkataramanan]
 
 
 Verilator 5.044 2026-01-01

include/verilated.cpp

@@ -442,6 +442,10 @@ WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) VL_MT_SAFE {
     return outwp;
 }
 
+double VL_RANDOM_RNG_D(VlRNG& rngr) VL_MT_UNSAFE {
+    return VL_CVT_D_Q(VL_RANDOM_RNG_Q(rngr));
+}
+
 WDataOutP VL_RANDOM_RNG_W(VlRNG& rngr, int obits, WDataOutP outwp) VL_MT_UNSAFE {
     for (int i = 0; i < VL_WORDS_I(obits); ++i) outwp[i] = rngr.rand64();
     // Last word is unclean

include/verilated_types.h

@@ -320,6 +320,7 @@ public:
 // These require the class object to have the thread safety lock
 inline IData VL_RANDOM_RNG_I(VlRNG& rngr) VL_MT_UNSAFE { return rngr.rand64(); }
 inline QData VL_RANDOM_RNG_Q(VlRNG& rngr) VL_MT_UNSAFE { return rngr.rand64(); }
+extern double VL_RANDOM_RNG_D(VlRNG& rngr) VL_MT_UNSAFE;
 extern WDataOutP VL_RANDOM_RNG_W(VlRNG& rngr, int obits, WDataOutP outwp) VL_MT_UNSAFE;
 
 //===================================================================

test_regress/t/t_randomize_real.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_randomize_real.v

@@ -0,0 +1,50 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+class Cls;
+  rand real m_real;
+endclass
+
+module test;
+  localparam LOOPS = 1000;
+
+  int negative;
+  int bitcounts[64];
+  int i;
+  bit [63:0] rbits;
+
+  initial begin
+    Cls c;
+    c = new;
+
+    repeat (LOOPS) begin
+      i = c.randomize();
+      `checkd(i, 1);
+
+      rbits = $realtobits(c.m_real);
+`ifdef TEST_VERBOSE
+      $display("%x %g", rbits, c.m_real);
+`endif
+
+      if (c.m_real < 0) negative++;
+      for (int b = 0; b < 64; ++b) begin
+        if (rbits[b]) bitcounts[b]++;
+      end
+    end
+
+    if (negative < LOOPS * 0.4) $error("Too few negative %0d", negative);
+    for (int b = 0; b < 64; ++b) begin
+      if (bitcounts[b] < LOOPS * 0.4) $error("Too few 1 bits at [%0d]: %0d", b, bitcounts[b]);
+    end
+    $finish;
+  end
+
+endmodule