luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,853 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

1157 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg c057490923 Delay chain should have same height cells as control logic to align supplies. 2021-05-05 15:45:28 -07:00
mrg f677c8a88d Fix predecoder offset after relocating bank offset 2021-05-05 14:44:05 -07:00
mrg 120c4de5ad Fix placement of delay chain to align with control logic rows. 2021-05-05 14:21:53 -07:00
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
Jesse Cirimelli-Low 1b53d12df2 don't double count spare col 2021-05-04 01:52:51 -07:00
Jesse Cirimelli-Low d0e9de1f13 fix port data spare col 2021-05-04 00:41:20 -07:00
Jesse Cirimelli-Low 93b264bc4c allow spare col number override 2021-05-03 21:59:05 -07:00
Jesse Cirimelli-Low 14e087a5eb offset bank coordinates 2021-05-03 15:51:53 -07:00
Jesse Cirimelli-Low 4377619bf6 fixed port_data typo 2021-05-03 14:39:51 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg fc6e6e1ec7 Add via when write driver supply is different layer 2021-04-28 15:16:26 -07:00
mrg 03e0c14ab2 Move write driver supply to m1 rather than pin layer 2021-04-28 10:13:33 -07:00
Jesse Cirimelli-Low 33e8bce79d dynamic predecode working 2021-04-25 01:22:36 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg 35fcb3f631 Abstracted LEF added. Params for array wordline layers. 2021-04-22 09:44:25 -07:00
mrg 15b0583ff2 Add custom parameter for wordline layer 2021-04-22 09:42:49 -07:00
mrg 419836411c Fix missing via for global wordlines. 2021-04-21 11:33:18 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg 439003e203 Respect the bus spacing parameter in predecoder. 2021-04-19 10:51:16 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low 2f1d7b879f make bank compatable with sky130 2021-04-14 15:09:25 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg 1c6de4591d Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 3ef56a29ea Bug fix 2021-01-13 13:56:22 -08:00
mrg bc9ab086e5 Clean up imports 2021-01-13 13:01:33 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 4fc0357282 Small readability edit to dff_buf 2021-01-04 13:16:23 -08:00
mrg 946ad66e7a Make width based on bitcell offsets, not number of columns 2020-12-18 09:22:10 -08:00
mrg 29880a0b5a Write mask and array supply pins on the ends 2020-12-17 15:25:19 -08:00
mrg e6ff73dbc1 Move supply pins for wmask and array to edge to avoid channel route congestion 2020-12-17 11:48:08 -08:00
mrg da48b8d98c Fix replica column bit index 2020-12-14 14:18:39 -08:00
mrg 47cc4cbfca Remove extra debug statement 2020-12-08 11:55:53 -08:00
mrg 0100ae57a3 Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
mrg bad1274bdb Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
mrg 705d8e3105 Fix wrong via starting layer 2020-12-01 17:12:35 -08:00
mrg 583a70c24e Fix select layer for column mux array 2020-12-01 15:20:44 -08:00
mrg a31e0dab02 Remove via-to-via path width hack 2020-12-01 13:27:32 -08:00
mrg a5b5f7c22b Change layer away from wordlines 2020-12-01 11:33:55 -08:00
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 27a652ac1b Fix bounding box of cap arrays 2020-11-20 16:54:53 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 1624d50ca9 Fix props bug again. 2020-11-13 20:35:19 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg bdda7c4f5f Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 857f5cb136 Fix copy pasta: decoder to predecode 2020-10-28 15:46:10 -07:00
mrg 00cb8a28d9 Fix supply layer query 2020-10-28 10:36:13 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 25495f3d94 getattr for bank parameters 2020-10-28 09:21:36 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg dc991cbcab Use pin of pgate to figure out supply layer. 2020-10-26 15:54:16 -07:00
mrg 38ba5fc10d Use pin of pgate to figure out supply layer. 2020-10-26 15:53:22 -07:00
mrg 804814d18d Add bitlines to dummy modules 2020-10-16 13:43:56 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
mrg 68d74737f7 Different bitcell and array supply pins 2020-10-13 07:41:21 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg c3d6be27be Fix argument name bug for remove wordlines 2020-10-08 16:58:38 -07:00
mrg 8d5db50062 Fix missing update for left RBL offset 2020-10-08 16:40:53 -07:00
mrg b0b15e8151 Fix indent bug that failed to create rbl wl pin labels. 2020-10-08 15:28:01 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg 483f6b187c RBL driver supply location differs for sky130 and other techs 2020-10-06 16:47:32 -07:00
mrg c2629edc1b Allow 16-way column mux 2020-10-06 16:27:02 -07:00
jcirimel 13e2a9f5f7 fix missed self.left_rbl refactor 2020-10-06 05:11:15 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 8ce23d7f17 Provide unique WL driver instance name 2020-10-01 07:17:32 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 066570bfeb Fix length of write driver 2020-09-29 16:51:55 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg b2dab486fc Add draft of path exclusion calls 2020-09-28 16:05:21 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 159c04a25d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-09-28 15:51:35 -07:00
mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins. 2020-09-28 14:49:33 -07:00
mrg 9c6d8d7aed Zjob to bottom. 2020-09-28 13:16:03 -07:00
mrg 5ab0d01779 Remove zjog and go with L shape. 2020-09-28 12:48:37 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
jcirimel de33ab3761 fix single port bitcell pattern 2020-09-22 15:08:53 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel 559dfbc7a6 single port bitcell array done 2020-09-16 05:46:14 -07:00
mrg e7ad22ff69 Separate WL via from bitell array to avoid grounded WLs 2020-09-15 13:38:28 -07:00
mrg 5e94d76127 Make global bitline only as wide as needed rather than whole array 2020-09-15 13:24:38 -07:00
mrg aff3cd2aab Update length of control bus 2020-09-15 09:49:00 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg f25b6ffa61 Make control bus height of port data 2020-09-14 15:42:17 -07:00
mrg 7b24d1f012 Use pins for write_driver dimensions 2020-09-14 14:42:28 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg deaaec1ede Fix width of write enable with spare columns 2020-09-14 13:09:45 -07:00
mrg c12720a93f Extend pin correct length in new array. 2020-09-14 12:53:59 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 4482c63d6f Fix sense amp offset index error 2020-09-11 17:12:29 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
mrg c58741c44f Updates to global array. 
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
 2020-09-10 16:44:54 -07:00
mrg 9c762634a5 Change default options for replica_bitcell_array 2020-09-10 15:11:48 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg f2313d0c73 Use default names for replica_column too 2020-09-10 12:04:46 -07:00
mrg 3c0707e5d1 Consistents of bl x port then br x port 2020-09-09 13:38:13 -07:00
mrg 3062aba214 Fix update to exclude bits with RBLs 2020-09-09 13:03:05 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
mrg 1269bf6e16 Global bitcell working 2020-09-04 13:06:58 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
mrg 1534295326 Ground dummy lines in replica bitcell array 2020-09-03 14:04:20 -07:00
mrg f6f6242d68 Ground dummy lines in replica bitcell array 2020-09-03 10:45:28 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg 4ec47d8ee1 Refactor global and local to be a bitcell_base_array 2020-09-01 11:59:01 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg da827d923f Merge branch 'wlbuffer' into dev 2020-08-26 10:00:34 -07:00
mrg c321d85595 Fix syntax error for dual port 2020-08-26 09:54:41 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bdb18b4cab Fix disconnected replica pins 2020-08-25 14:51:49 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 3f45d10797 fix column decoder 2020-08-25 02:46:16 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg 593a98e29a Update local bitcell array for dual port 2020-08-19 11:35:55 -07:00
jcirimel b7ef5496c4 decoder drc clean 2020-08-19 00:39:55 -07:00
mrg e215c0e016 Drafting global bitcell array 2020-08-18 16:30:55 -07:00
mrg 5776788574 Order of wordlines and bitlines in bank 2020-08-18 16:30:38 -07:00
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg e3e4bac922 Fix replica bitcell array for right only RBL 2020-08-18 15:47:52 -07:00
mrg 59d65c46c3 Fix bug in not adding RBLs in local bitcell array 2020-08-18 15:11:10 -07:00
mrg 2643a96f97 Order inputs wordline, bitline, supply 2020-08-18 14:29:36 -07:00
mrg f98fbb175b Merge branch 'wlbuffer' into dev 2020-08-18 10:06:52 -07:00
mrg e37a9234cc Update replica column call to new refactor 2020-08-18 09:14:50 -07:00
mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-18 09:01:41 -07:00
mrg bc974ff78e Update replica column unit tests for new refactor 2020-08-18 08:56:24 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 94bfad4113 Horizontal gnd vias for unused array inputs 2020-08-17 13:24:34 -07:00
mrg bddb251a84 More room for power contacts 2020-08-17 12:32:44 -07:00
mrg 35a1b00aa0 Extra space for unused wl contacts 2020-08-14 14:23:40 -07:00
mrg 170e3feb7d Fix order of replica wordlines and bitlines 2020-08-14 14:14:49 -07:00
mrg 2ac04efe2e Must connect for replica cells other than top/bottom 2020-08-13 16:26:19 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg b07f30cb9e Missing output via in control logic 2020-06-30 16:23:07 -07:00
mrg 011ac2fc05 Don't route to clk to perimeter on m2 2020-06-30 13:57:45 -07:00
mrg a48ea52253 Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
mrg eb11ac22f3 Widen pitch of control bus in bank. 2020-06-30 10:58:09 -07:00
mrg 372a8a728e Off by one error in channel spacing 2020-06-29 16:47:34 -07:00
mrg 459e3789b8 Change control layers in sky130. 2020-06-29 16:23:25 -07:00
mrg bec948dcc3 Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 1bc0775810 Only add pins to periphery 2020-06-29 10:03:24 -07:00
mrg 5285468380 All bitcells need a vdd/gnd pin 2020-06-28 15:09:47 -07:00
mrg 051c8d8697 Only add bitcells to dummy and replica rows and columns (the perimeter) 2020-06-28 14:47:54 -07:00
mrg 225fc69420 Use preferred routing direction 2020-06-28 14:29:12 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg 609aa98c8b Move write mask pin to left of cell to avoid sense amp 2020-06-27 08:21:53 -07:00
mrg 2bd498c39c Change precharge layer to m3 2020-06-27 08:21:30 -07:00
mrg c07e20cbe4 Move mux select from li to m2 in sky130 2020-06-26 14:27:16 -07:00
mrg f57eeb88eb PEP8 cleanup, multiple vdd/gnd support 2020-06-26 11:47:55 -07:00
mrg e23d41c1d4 PEP8 cleanup 2020-06-26 11:47:35 -07:00
mrg 66df659ad4 Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
mrg f84ee04fa9 Single bank passing. 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
 2020-06-25 14:03:59 -07:00
mrg 93d65e84e1 Fix power pin layer problems in delay line 2020-06-24 10:26:49 -07:00
Joey Kunzler 4e83e8c648 added contact to locali for wmask 2020-06-23 18:13:17 -07:00
mrg cfa234a4d0 Extra space between decoders for well spacing 2020-06-23 15:39:42 -07:00
mrg cd23b31ab4 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-22 12:55:45 -07:00
mrg 0926eab9f5 PEP8 formatting 2020-06-22 12:55:18 -07:00
Joey Kunzler 208c652653 added error for sky130 with invalid x mirroring (for lvs) 2020-06-19 13:59:33 -07:00
mrg abb5ff7bae Separate route conditions for s8 2020-06-15 10:30:27 -07:00
mrg e331d6fae8 Permute bus order to avoid conflict in control_logic 2020-06-15 10:25:53 -07:00
mrg 79b3b9a8b0 Switch input/output layers for predecodes 2020-06-15 10:06:04 -07:00
mrg 02352c35d7 Fix hard coded layer in wmask 2020-06-14 17:10:32 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg e9780ea599 Add non-preferred directions for channel routes 2020-06-11 15:03:36 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg bfd1abc79f Replica column pins start at 0 height. 2020-06-10 14:58:55 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg 77fb7017c4 Merge branch 'tech_migration' into dev 2020-06-08 12:54:41 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
Aditi Sinha 300522a1a8 Change spare enable pins offset to lower right 2020-06-08 14:31:46 +00:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 0837432d45 Wordline route layers and (optional) via. 2020-06-05 16:47:22 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg 7aafa43897 Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
mrg 249b5355ba Adjust rbl route 2020-06-03 17:08:04 -07:00
mrg 3927c62e32 Undo extra space due to nwell spacing 2020-06-03 16:39:33 -07:00
mrg 3b1fe26d25 Spacing between decoder and driver for s8 2020-06-03 14:33:30 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg fdf51c5a00 Add port option to precharge array 2020-06-02 11:44:22 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg 45b0601e4b Fix via directions in s8 col mux 2020-06-02 11:43:31 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
Joey Kunzler b00163e4e1 lvs fix for regression tests 2020-05-29 13:50:34 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha c14190c5aa Changes in control logic for spare columns 2020-05-14 10:41:54 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Aditi Sinha 5c50cf234b Fixed lvs errors for spare columns 2020-05-09 07:56:19 +00:00
Aditi Sinha e30938fb66 Spare columns working at bank level 2020-05-03 15:23:30 +00:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg f1c1adc9bd Simplify supply contacts in delay chain. 2020-04-21 16:12:54 -07:00
mrg 0f6998a1c5 PEP8 cleanup 2020-04-21 15:36:38 -07:00
mrg cd66ddb37c Add supply rails to dff array. PEP8 cleanup. 2020-04-21 15:21:29 -07:00
mrg f6135f3471 PEP8 formatting 2020-04-20 16:38:30 -07:00
mrg 7995451cbb PEP8 formatting 2020-04-20 14:45:18 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
mrg 843e9414df Parameterize vdd and gnd pin in write driver array. 2020-04-16 11:28:35 -07:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
mrg 9d2902de9e Conditional well spacing 2020-04-15 15:55:49 -07:00
mrg e95c97d7a5 PEP8 cleanup 2020-04-15 14:29:43 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
mrg 0941ebc3da Fix well spacing issue 2020-04-14 14:08:07 -07:00
mrg 32d190b8b1 Jog connection on M1 for bank select. 2020-04-14 12:15:56 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
mrg 8a55c223df Use single height for netlist_only mode 2020-04-09 09:48:54 -07:00
mrg 58fbc5351a Change rows to outputs in hierarchical decoder 2020-04-08 17:05:16 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Jesse Cirimelli-Low b59c789dec remove whitespace 2020-04-05 03:58:26 -07:00
Jesse Cirimelli-Low 8b33cb519f Merge branch 'dev' into custom_mod 2020-04-03 17:05:56 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
Jesse Cirimelli-Low cdf0315a90 Merge branch 'dev' into custom_mod 2020-04-01 15:35:33 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
Jesse Cirimelli-Low 341bde7a48 Merge branch 'dev' into custom_mod 2020-03-26 02:40:37 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 1a2efd77ad Move rbl route away from bitcell array 2020-03-06 09:48:20 -08:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 9c1f0657dd PEP8 Formatting 2020-03-05 11:58:36 -08:00
mrg 7adeef6c9e PEP8 Formatting 2020-03-05 10:21:18 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
Jesse Cirimelli-Low f62016ad9f revert dff_buf for no body contact 2020-03-03 12:40:08 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
Bastian Koppelmann 0e641bf905 Remove write_driver_array.py.orig 
this was the remainder of applying a diff using "patch". To avoid this
mistake, add the filetypes created by "patch" to the .gitignore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-21 13:29:43 +01:00
Aditi Sinha 694ea5c20e Characterization for extra rows 2020-02-20 17:31:58 +00:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Matt Guthaus da4c69ab98 Merge branch 'pin-pull3' into dev 2020-02-20 09:07:58 -08:00
Hunter Nichols c1cb6bf512 Changed layout input names of s_en AND gate to match the schematic 2020-02-19 23:32:11 -08:00
Hunter Nichols 843fce41d7 Fixed issues with sen control logic for read ports. 2020-02-19 03:06:11 -08:00
Bastian Koppelmann 76256a2f1b sense_amp: Allow custom pin names 
we don't want to propagate the sense amp's bl/br names out of the
sense_amp_array. Thus the sense_amp_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:12 +01:00
Bastian Koppelmann 680dc6d2c7 sense_amp/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:06 +01:00
Bastian Koppelmann 9a12b68680 write_driver: Allow custom pin names 
we don't want to propagate the write driver bl/br names out of the
write_driver_array. Thus the write_driver_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:25:00 +01:00
Bastian Koppelmann c06cb2bfc2 write_driver/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:23:26 +01:00
Bastian Koppelmann 656fdd1008 port_data: Refactor channel_route/connect_bitlines() 
both functions share a lot of code and are passing around a lot of data
under similar names (inst1, inst1_start_bit, inst1_bl_name, ...). Thus
we group all these elements in a named tuple to ease passing around
these elements.

All callers of channel_route/connect_bitlines() either pass in the bl/br
names or rely on "br_{}"/"bl_{}" as defaults. These hard coded values
should be determined by the instances. Thus we get the bitline names
based on the instances passed in. The callers only provide a template
string, to take care of the case that bitlines are called "bl_out_{}".

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:20:03 +01:00
Bastian Koppelmann 5e1f64c8f9 modules/port_data: Add get_bl/br_name method 
if we rely on the names of the submodules (sense_amp_array,
write_driver_array, etc.) for port_data's pins, we get into trouble on
multiport SRAMs. To avoid this we use explicit names for br/bl depending
on the port number in port_data. Now each submodule does no longer need to
figure out the right name depending on the port number.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:18:32 +01:00
Bastian Koppelmann f6302caeac replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 
this allows us to override the bl/br/wl names of each bitcell.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:37:47 +01:00
Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names 
before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Bastian Koppelmann 64bf93e4e5 bank: Connect instances by their individual bl/br names 
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Jesse Cirimelli-Low a23f72d5a3 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00