mirror of https://github.com/VLSIDA/OpenRAM.git
Add missing vias by using via stack function
This commit is contained in:
mrg
parent
4a67f7dc71
commit
82dc937768
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@ -534,11 +534,14 @@ class port_data(design.design):
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else:
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start_bit=0
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self.channel_route_bitlines(inst1=inst1,
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inst1_bls_template=inst1_bls_templ,
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inst2=inst2,
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num_bits=self.word_size,
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inst1_start_bit=start_bit)
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("SA to precharge")
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self.connect_bitlines(inst1=inst1,
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inst1_bls_template=inst1_bls_templ,
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inst2=inst2,
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num_bits=self.word_size,
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inst1_start_bit=start_bit)
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def route_write_driver_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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@ -558,10 +561,13 @@ class port_data(design.design):
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else:
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start_bit=0
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self.channel_route_bitlines(inst1=inst1, inst2=inst2,
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num_bits=self.word_size,
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inst1_bls_template=inst1_bls_templ,
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inst1_start_bit=start_bit)
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("WD to precharge")
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self.connect_bitlines(inst1=inst1, inst2=inst2,
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num_bits=self.word_size,
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inst1_bls_template=inst1_bls_templ,
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inst1_start_bit=start_bit)
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def route_write_driver_to_sense_amp(self, port):
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""" Routing of BL and BR between write driver and sense amp """
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@ -569,11 +575,12 @@ class port_data(design.design):
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inst1 = self.write_driver_array_inst
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inst2 = self.sense_amp_array_inst
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# These should be pitch matched in the cell library,
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# but just in case, do a channel route.
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self.channel_route_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.word_size)
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("WD to SA")
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self.connect_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.word_size)
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def route_bitline_pins(self):
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""" Add the bitline pins for the given port """
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@ -676,10 +683,9 @@ class port_data(design.design):
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Route the bl and br of two modules using the channel router.
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"""
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bot_inst_group, top_inst_group = self._group_bitline_instances(
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inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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bot_inst_group, top_inst_group = self._group_bitline_instances(inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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# Channel route each mux separately since we don't minimize the number
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# of tracks in teh channel router yet. If we did, we could route all the bits at once!
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@ -688,13 +694,8 @@ class port_data(design.design):
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bottom_names = self._get_bitline_pins(bot_inst_group, bit)
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top_names = self._get_bitline_pins(top_inst_group, bit)
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if bottom_names[0].layer == "m2":
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bitline_dirs = ("H", "V")
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elif bottom_names[0].layer == "m1":
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bitline_dirs = ("V", "H")
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route_map = list(zip(bottom_names, top_names))
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack, bitline_dirs)
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
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def connect_bitlines(self, inst1, inst2, num_bits,
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inst1_bls_template="{inst}_{bit}",
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@ -707,26 +708,23 @@ class port_data(design.design):
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in the middle between the two modules (if needed).
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"""
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bot_inst_group, top_inst_group = self._group_bitline_instances(
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inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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bot_inst_group, top_inst_group = self._group_bitline_instances(inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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for col in range(num_bits):
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print(col)
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bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col)
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top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col)
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bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc()
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top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc()
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yoffset = 0.5 * (top_bl.y + bot_bl.y)
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self.add_path("m2", [bot_bl,
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vector(bot_bl.x, yoffset),
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vector(top_bl.x, yoffset),
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top_bl])
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self.add_path("m2", [bot_br,
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vector(bot_br.x, yoffset),
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vector(top_br.x, yoffset),
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top_br])
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print("BL", bot_bl, top_bl)
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print(bot_bl_pin, top_bl_pin)
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print("BR", bot_br, top_br)
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print(bot_br_pin, top_br_pin)
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self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V")
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self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V")
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def graph_exclude_precharge(self):
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"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
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@ -105,21 +105,19 @@ class precharge(design.design):
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# center of vdd rail
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pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
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self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos])
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self.add_path(self.bitline_layer, [pmos_pin.center(), pmos_vdd_pos])
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# if enable is not on M1, the supply can be
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if self.en_layer != "m1":
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self.add_via_center(layers=self.m1_stack,
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offset=pmos_vdd_pos)
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self.add_via_stack_center(from_layer=self.bitline_layer,
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to_layer=self.en_layer,
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offset=pmos_vdd_pos)
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self.add_power_pin("vdd",
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self.well_contact_pos,
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directions=("V", "V"))
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# Hack for li layers
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if hasattr(self, "li_stack"):
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self.add_via_center(layers=self.li_stack,
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offset=self.well_contact_pos)
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self.add_via_stack_center(from_layer=pmos_pin.layer,
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to_layer=self.bitline_layer,
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offset=pmos_pin.center(),
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directions=("V", "V"))
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def create_ptx(self):
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"""
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@ -199,14 +197,9 @@ class precharge(design.design):
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# midway in the 4 M2 tracks
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offset = self.lower_pmos_inst.get_pin("G").ul() \
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+ vector(0, 0.5 * self.m2_pitch)
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self.add_via_center(layers=self.poly_stack,
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offset=offset)
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if self.en_layer == "m2":
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self.add_via_center(layers=self.m1_stack,
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offset=offset)
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if hasattr(self, "li_stack"):
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self.add_via_center(layers=self.li_stack,
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offset=offset)
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self.add_via_stack_center(from_layer="poly",
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to_layer=self.en_layer,
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offset=offset)
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# adds the en rail on metal1
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self.add_layout_pin_segment_center(text="en_bar",
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@ -225,13 +218,13 @@ class precharge(design.design):
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self.nwell_extend_active
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self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \
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vector(0, offset_height)
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self.add_via_center(layers=self.active_stack,
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offset=self.well_contact_pos,
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implant_type="n",
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well_type="n")
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if hasattr(self, "li_stack"):
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self.add_via_center(layers=self.li_stack,
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offset=self.well_contact_pos)
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self.well_contact = self.add_via_center(layers=self.active_stack,
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offset=self.well_contact_pos,
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implant_type="n",
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well_type="n")
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self.add_via_stack_center(from_layer=self.active_stack[2],
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to_layer=self.bitline_layer,
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offset=self.well_contact_pos)
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self.height = self.well_contact_pos.y + contact.active_contact.height + self.m1_space
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@ -288,31 +281,19 @@ class precharge(design.design):
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Adds contacts/via from metal1 to metal2 for bit-lines
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"""
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# No contacts needed if M1
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if self.bitline_layer == "m1":
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return
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# BL
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lower_pin = self.lower_pmos_inst.get_pin("S")
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self.lower_via = self.add_via_center(layers=self.m1_stack,
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offset=lower_pin.center(),
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directions=("V", "V"))
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for lower_pin in [self.lower_pmos_inst.get_pin("S"), self.lower_pmos_inst.get_pin("D")]:
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self.add_via_stack_center(from_layer=lower_pin.layer,
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to_layer=self.bitline_layer,
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offset=lower_pin.center(),
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directions=("V", "V"))
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lower_pin = self.lower_pmos_inst.get_pin("D")
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self.lower_via = self.add_via_center(layers=self.m1_stack,
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offset=lower_pin.center(),
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directions=("V", "V"))
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# BR
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upper_pin = self.upper_pmos1_inst.get_pin("S")
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self.upper_via2 = self.add_via_center(layers=self.m1_stack,
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offset=upper_pin.center(),
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directions=("V", "V"))
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upper_pin = self.upper_pmos2_inst.get_pin("D")
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self.upper_via2 = self.add_via_center(layers=self.m1_stack,
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offset=upper_pin.center(),
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directions=("V", "V"))
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for upper_pin in [self.upper_pmos1_inst.get_pin("S"), self.upper_pmos2_inst.get_pin("D")]:
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self.add_via_stack_center(from_layer=upper_pin.layer,
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to_layer=self.bitline_layer,
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offset=upper_pin.center(),
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directions=("V", "V"))
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def connect_pmos(self, pmos_pin, bit_xoffset):
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"""
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