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Fix wrong via starting layer

This commit is contained in:
mrg 2020-12-01 17:12:35 -08:00
parent f320017b86
commit 705d8e3105
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/port_address.py
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@ -91,7 +91,7 @@ class port_address(design.design):
rbl_b_pin = self.rbl_driver_inst.get_pin("B")
rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0)
self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc])
self.add_power_pin("vdd", rbl_loc)
self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer)
def route_pins(self):
for row in range(self.addr_size):