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fix for replica column mirroring over y

This commit is contained in:
Joey Kunzler 2020-05-28 20:31:21 -07:00
parent 7505fa5aef
commit 218a553ac5
2 changed files with 7 additions and 5 deletions
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6
compiler/modules/replica_bitcell_array.py
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@ -91,14 +91,16 @@ class replica_bitcell_array(design.design):
# Replica bitlines
self.replica_columns = {}
for bit in range(self.left_rbl+self.right_rbl):
# Creating left_rbl
if bit<self.left_rbl:
replica_bit = bit+1
# dummy column
column_offset = 1
column_offset = self.left_rbl - bit
# Creating right_rbl
else:
replica_bit = bit+self.row_size+1
# dummy column + replica column + bitcell colums
column_offset = 3 + self.row_size
column_offset = self.left_rbl - bit + self.row_size
self.replica_columns[bit] = factory.create(module_type="replica_column",
rows=self.row_size,
left_rbl=self.left_rbl,

6
compiler/tests/14_replica_bitcell_1rw_1r_array_test.py
View File

@ -28,9 +28,9 @@ class replica_bitcell_array_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
# debug.info(2, "Testing 4x4 array for cell_1rw_1r")
# a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0,1])
# self.local_check(a)
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0,1])
self.local_check(a)
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1])