mirror of https://github.com/VLSIDA/OpenRAM.git
Switch input/output layers for predecodes
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@ -83,9 +83,9 @@ class hierarchical_predecode(design.design):
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self.bus_directions = None
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self.bus_pitch = self.m1_pitch
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self.bus_space = 1.5 * self.m1_space
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self.input_layer = "li"
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self.output_layer = "m2"
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self.output_layer_pitch = self.m2_pitch
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self.input_layer = "m2"
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self.output_layer = "li"
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self.output_layer_pitch = self.li_pitch
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else:
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self.bus_layer = "m2"
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self.bus_directions = None
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@ -234,12 +234,12 @@ class hierarchical_predecode(design.design):
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in_pin = "in_{}".format(inv_num)
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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inv_out_pos = inv_out_pin.rc()
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inv_out_pos = inv_out_pin.lr()
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# add output so that it is just below the vdd or gnd rail
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# since this is where the p/n devices are and there are no
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# pins in the and gates.
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if OPTS.tech_name == "sky130":
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if False and OPTS.tech_name == "sky130":
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rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
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self.add_path(self.output_layer, [inv_out_pos, rail_pos])
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else:
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