mirror of https://github.com/VLSIDA/OpenRAM.git
Update interface of RBL array
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mrg
parent
b1e55f9072
commit
99e252d6d4
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@ -382,9 +382,8 @@ class bank(design.design):
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows,
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left_rbl=1,
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right_rbl=1 if len(self.all_ports)>1 else 0,
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bitcell_ports=self.all_ports)
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rbl=[1, 1 if len(self.all_ports)>1 else 0])
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self.add_mod(self.bitcell_array)
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if(self.num_banks > 1):
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@ -16,13 +16,11 @@ class global_bitcell_array(bitcell_base_array):
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Creates a global bitcell array with a number
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of local arrays of a sizes given by a tuple in the list.
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"""
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def __init__(self, sizes, name=""):
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# Each bank will have the same number of rows
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self.rows = sizes[0][0]
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for (r, c) in sizes:
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debug.check(r[0] == self.rows, "Cannot have non-uniform number of rows in global array.")
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def __init__(self, rows, cols, ports, add_replica, name=""):
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# The total of all columns will be the number of columns
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self.cols = sum(x[1] for x in sizes)
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self.cols = sum(cols)
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self.local_cols = cols
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self.rows = rows
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self.sizes = sizes
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super().__init__(rows=self.rows, cols=self.cols, name=name)
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@ -49,9 +47,15 @@ class global_bitcell_array(bitcell_base_array):
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def add_modules(self):
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""" Add the modules used in this design """
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self.local_mods = []
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for (row, col) in self.sizes:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col)
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self.add_mod(la)
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for i, col in enumerate(self.local_cols):
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if i==self.add_replica[0]:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True)
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elif len(self.add_replica)==2 and i==self.add_replica[2]:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True)
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else:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, add_replica=False)
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self.add_mod(la)
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self.local_mods.append(la)
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def create_instances(self):
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@ -18,15 +18,16 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, add_replica=True, name=""):
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def __init__(self, rows, cols, rbl, add_rbl=None, name=""):
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super().__init__(name, rows, cols, 0)
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debug.info(2, "create local array of size {} rows x {} cols words".format(rows,
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cols + left_rbl + right_rbl))
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cols + sum(rbl)))
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self.rows = rows
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self.cols = cols
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self.add_replica=add_replica
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self.all_ports = ports
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self.rbl = rbl
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if add_rbl == None:
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self.add_rbl = rbl
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -62,10 +63,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.cols,
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rows=self.rows,
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left_rbl=1,
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right_rbl=1 if len(self.all_ports)>1 else 0,
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bitcell_ports=self.all_ports,
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add_replica=self.add_replica)
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rbl=self.rbl)
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self.add_mod(self.bitcell_array)
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self.wl_array = factory.create(module_type="wordline_buffer_array",
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@ -21,34 +21,32 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, left_rbl, right_rbl, bitcell_ports, name, add_replica=True):
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def __init__(self, rows, cols, rbl, name, add_rbl=None):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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self.bitcell_ports = bitcell_ports
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# If set to false, we increase the height for the replica wordline row, but don't
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# actually add the column to this array. This is so the height matches other
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# banks that have the replica columns.
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# Number of replica columns to actually add
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if add_replica:
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self.add_left_rbl = self.left_rbl
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self.add_right_rbl = self.right_rbl
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# This is how many RBLs are in all the arrays
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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# This is how many RBLs are added to THIS array
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if add_rbl == None:
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self.add_left_rbl = rbl[0]
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self.add_right_rbl = rbl[1]
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else:
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self.add_left_rbl = 0
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self.add_right_rbl = 0
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self.add_left_rbl = add_rbl[0]
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self.add_right_rbl = add_rbl[1]
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for a, b in zip(add_rbl, rbl):
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debug.check(a <= b,
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"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl + right_rbl <= len(self.all_ports),
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debug.check(sum(rbl) <= len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl + right_rbl <= len(self.bitcell_ports),
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"Bitcell ports must match total RBLs.")
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = 2 + self.left_rbl + self.right_rbl
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self.extra_rows = 2 + sum(rbl)
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# Two dummy cols plus replica if we add the column
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self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
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@ -198,7 +196,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))]
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right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))]
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# Keep track of the left pins that are the RBL
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self.replica_bl_names[port]=left_names[self.bitcell_ports[port]]
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self.replica_bl_names[port]=left_names[self.all_ports[port]]
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# Interleave the left and right lists
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bitline_names = [x for t in zip(left_names, right_names) for x in t]
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self.replica_bitline_names[port] = bitline_names
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@ -23,11 +23,11 @@ class local_bitcell_array_test(openram_test):
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globals.init_openram(config_file)
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debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
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a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, ports=[0], add_replica=False)
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a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[0, 0])
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self.local_check(a)
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debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
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a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
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a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0])
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self.local_check(a)
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globals.end_openram()
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@ -28,19 +28,15 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
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a = factory.create(module_type="replica_bitcell_array",
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cols=4,
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rows=4,
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left_rbl=1,
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right_rbl=1,
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bitcell_ports=[0, 1],
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add_replica=False)
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rbl=[1, 1],
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add_rbl=[0, 0])
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self.local_check(a)
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debug.info(2, "Testing 4x4 array for cell_1rw_1r")
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a = factory.create(module_type="replica_bitcell_array",
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cols=4,
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rows=4,
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left_rbl=1,
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right_rbl=1,
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bitcell_ports=[0, 1])
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rbl=[1, 1])
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self.local_check(a)
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@ -50,9 +46,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
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a = factory.create(module_type="replica_bitcell_array",
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cols=4,
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rows=4,
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left_rbl=2,
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right_rbl=0,
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bitcell_ports=[0, 1])
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rbl=[2, 0])
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self.local_check(a)
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globals.end_openram()
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@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test):
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factory.reset()
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debug.info(2, "Testing 4x4 array for bitcell")
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0])
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self.local_check(a)
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globals.end_openram()
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@ -25,15 +25,15 @@ class replica_column_test(openram_test):
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globals.setup_bitcell()
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
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self.local_check(a)
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
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self.local_check(a)
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2)
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a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
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self.local_check(a)
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globals.end_openram()
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@ -20,15 +20,15 @@ class replica_column_test(openram_test):
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globals.init_openram(config_file)
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
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self.local_check(a)
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
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self.local_check(a)
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debug.info(2, "Testing replica column for 6t_cell")
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a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2)
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a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
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self.local_check(a)
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globals.end_openram()
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@ -27,7 +27,7 @@ class replica_pbitcell_array_test(openram_test):
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OPTS.num_w_ports = 0
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debug.info(2, "Testing 4x4 array for pbitcell")
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1])
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 1])
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self.local_check(a)
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OPTS.bitcell = "pbitcell"
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@ -39,7 +39,7 @@ class replica_pbitcell_array_test(openram_test):
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factory.reset()
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debug.info(2, "Testing 4x4 array for pbitcell")
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0])
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self.local_check(a)
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globals.end_openram()
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