mirror of https://github.com/VLSIDA/OpenRAM.git
Remove extra debug statement
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@ -390,7 +390,6 @@ class replica_bitcell_array(bitcell_base_array):
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# These grow up, away from the array
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for bit in range(self.rbl[1]):
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dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
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import pdb; pdb.set_trace()
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
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mirror="MX" if (self.row_size + bit) % 2 else "R0")
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