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Merge branch 'wlbuffer' into dev

This commit is contained in:
mrg 2020-08-26 10:00:34 -07:00
parent 652f160aca c321d85595
commit da827d923f
4 changed files with 37 additions and 17 deletions
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16
compiler/modules/bank.py
View File

@ -392,21 +392,9 @@ class bank(design.design):
# vdd
# gnd
temp = []
temp.extend(self.bitcell_array.get_dummy_bitline_names(0))
temp.extend(self.bitcell_array.get_rbl_bitline_names(0))
temp.extend(self.bitcell_array.get_bitline_names())
if len(self.all_ports) > 1:
temp.extend(self.bitcell_array.get_rbl_bitline_names(1))
temp.extend(self.bitcell_array.get_dummy_bitline_names(1))
temp = self.bitcell_array.get_all_bitline_names()
wordline_names = self.bitcell_array.get_dummy_wordline_names(0)
wordline_names.extend(self.bitcell_array.get_rbl_wordline_names(0))
wordline_names.extend(self.bitcell_array.get_wordline_names())
if len(self.all_ports) > 1:
wordline_names.extend(self.bitcell_array.get_rbl_wordline_names(1))
wordline_names.extend(self.bitcell_array.get_dummy_wordline_names(1))
wordline_names = self.bitcell_array.get_all_wordline_names()
# Rename the RBL WL to the enable name
for port in self.all_ports:

2
compiler/modules/local_bitcell_array.py
View File

@ -104,7 +104,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
# Connect unused RBL WL to gnd
array_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("rbl")])
dummy_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("dummy")])
rbl_wl_names = set([self.bitcell_array.get_rbl_wordline_names(x) for x in self.all_ports])
rbl_wl_names = set([x for port in self.all_ports for x in self.bitcell_array.get_rbl_wordline_names(port)])
self.gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names)
self.all_array_wordline_inputs = [x + "i" if x not in self.gnd_wl_names else "gnd" for x in self.bitcell_array.get_wordline_names()]

34
compiler/modules/replica_bitcell_array.py
View File

@ -471,12 +471,44 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
return self.rbl_bitline_names[port]
def get_bitline_names(self, port=None):
""" Return the BL for the given RBL port """
""" Return the regular bitlines for the given port or all"""
if port == None:
return self.all_bitline_names
else:
return self.bitline_names[port]
def get_all_bitline_names(self):
""" Return ALL the bitline names (including dummy and rbl) """
temp = []
temp.extend(self.get_dummy_bitline_names(0))
temp.extend(self.get_rbl_bitline_names(0))
temp.extend(self.get_bitline_names())
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_bitline_names(1))
temp.extend(self.get_dummy_bitline_names(1))
return temp
def get_wordline_names(self, port=None):
""" Return the regular wordline names """
if port == None:
return self.all_wordline_names
else:
return self.wordline_names[port]
def get_all_wordline_names(self, port=None):
""" Return all the wordline names """
temp = []
temp.extend(self.get_dummy_wordline_names(0))
temp.extend(self.get_rbl_wordline_names(0))
if port == None:
temp.extend(self.all_wordline_names)
else:
temp.extend(self.wordline_names[port])
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
temp.extend(self.get_dummy_wordline_names(1))
return temp
def get_dummy_wordline_names(self, port=None):
"""
Return the ACTIVE WL for the given dummy port.

2
compiler/tests/15_local_bitcell_array_test.py
View File

@ -15,7 +15,7 @@ from sram_factory import factory
import debug
@unittest.skip("SKIPPING 05_local_bitcell_array_test")
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_test(openram_test):
def runTest(self):