mirror of https://github.com/VLSIDA/OpenRAM.git
Remove prints
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parent
82dc937768
commit
496a24389c
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@ -536,7 +536,6 @@ class port_data(design.design):
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("SA to precharge")
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self.connect_bitlines(inst1=inst1,
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inst1_bls_template=inst1_bls_templ,
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inst2=inst2,
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@ -563,7 +562,6 @@ class port_data(design.design):
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("WD to precharge")
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self.connect_bitlines(inst1=inst1, inst2=inst2,
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num_bits=self.word_size,
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inst1_bls_template=inst1_bls_templ,
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@ -577,7 +575,6 @@ class port_data(design.design):
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# This could be a channel route, but in some techs the bitlines
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# are too close together.
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print("WD to SA")
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self.connect_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.word_size)
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@ -713,16 +710,11 @@ class port_data(design.design):
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inst2_bls_template, inst2_start_bit)
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for col in range(num_bits):
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print(col)
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bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col)
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top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col)
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bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc()
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top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc()
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print("BL", bot_bl, top_bl)
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print(bot_bl_pin, top_bl_pin)
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print("BR", bot_br, top_br)
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print(bot_br_pin, top_br_pin)
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self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V")
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self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V")
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