mirror of https://github.com/VLSIDA/OpenRAM.git
Fix placement of delay chain to align with control logic rows.
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@ -391,9 +391,9 @@ class control_logic(design.design):
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def place_delay(self, row):
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""" Place the replica bitline """
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debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.")
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# It is flipped on X axis
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y_off = (row + self.delay_chain.rows) * self.and2.height
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y_off = row * self.and2.height + self.delay_chain.height
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# Add the RBL above the rows
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# Add to the right of the control rows and routing channel
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