mirror of https://github.com/VLSIDA/OpenRAM.git
Ground dummy lines in replica bitcell array
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mrg
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4ec47d8ee1
commit
f6f6242d68
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@ -218,14 +218,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.wordline_names = []
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# Replica wordlines by port
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self.rbl_wordline_names = []
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# Dummy wordlines by bot/top
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self.dummy_row_wordline_names = []
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dummy_row_wordline_names = ["dummy_" + x for x in self.col_cap.get_wordline_names()]
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for loc in ["bot", "top"]:
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wordline_names = ["{0}_{1}".format(wl_name, loc) for wl_name in dummy_row_wordline_names]
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self.dummy_row_wordline_names.append(wordline_names)
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self.all_dummy_row_wordline_names = [x for sl in self.dummy_row_wordline_names for x in sl]
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self.dummy_row_wordline_names = ["gnd"] * len(self.col_cap.get_wordline_names())
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for port in range(self.left_rbl + self.right_rbl):
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wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports]
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@ -239,21 +233,19 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[0])
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names)
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for p in range(self.left_rbl):
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self.replica_array_wordline_names.extend(self.rbl_wordline_names[p])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for p in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.replica_array_wordline_names.extend(self.rbl_wordline_names[p])
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[1])
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self.replica_array_wordline_names.extend(self.dummy_row_wordline_names)
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self.add_pin_list(self.dummy_row_wordline_names[0], "INPUT")
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for port in range(self.left_rbl):
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self.add_pin_list(self.rbl_wordline_names[port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.add_pin_list(self.rbl_wordline_names[port], "INPUT")
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self.add_pin_list(self.dummy_row_wordline_names[1], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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@ -287,10 +279,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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self.connect_inst(self.dummy_row_wordline_names[0] + supplies)
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self.connect_inst(self.dummy_row_wordline_names + supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap))
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self.connect_inst(self.dummy_row_wordline_names[1] + supplies)
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self.connect_inst(self.dummy_row_wordline_names + supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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@ -316,12 +308,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.add_end_caps()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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self.translate_all(self.bitcell_offset.scale(-1 - self.add_left_rbl, -1 - self.left_rbl))
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self.add_layout_pins()
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self.route_unused_wordlines()
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self.add_boundary()
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self.DRC_LVS()
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@ -395,17 +390,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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width=pin.width(),
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height=self.height)
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# Dummy wordlines
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for (names, inst) in zip(self.dummy_row_wordline_names, self.dummy_row_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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# It's always a single row
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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@ -459,6 +443,27 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap.get_wordline_names():
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pin = inst.get_pin(wl_name)
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pin_layer = pin.layer
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layer_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
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left_pin_loc = vector(self.dummy_col_insts[0].lx(), pin.cy())
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right_pin_loc = vector(self.dummy_col_insts[1].rx(), pin.cy())
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# Place the pins a track outside of the array
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left_loc = left_pin_loc - vector(layer_pitch, 0)
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right_loc = right_pin_loc + vector(layer_pitch, 0)
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self.add_power_pin("gnd", left_loc, directions=("H", "H"))
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self.add_power_pin("gnd", right_loc, directions=("H", "H"))
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# Add a path to connect to the array
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self.add_path(pin_layer, [left_loc, left_pin_loc])
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self.add_path(pin_layer, [right_loc, right_pin_loc])
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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height = 0
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