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Add decoder4x16

This commit is contained in:
mrg 2020-10-02 15:52:09 -07:00
parent 1fc4040607
commit f8146e3f69
4 changed files with 20 additions and 14 deletions
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11
compiler/modules/hierarchical_predecode.py
View File

@ -44,7 +44,7 @@ class hierarchical_predecode(design.design):
def add_modules(self):
""" Add the INV and AND gate modules """
debug.check(self.number_of_inputs < 4,
debug.check(self.number_of_inputs <= 4,
"Invalid number of predecode inputs: {}".format(self.number_of_inputs))
if self.column_decoder:
@ -203,6 +203,7 @@ class hierarchical_predecode(design.design):
pin = top_and_gate.get_pin("D")
else:
debug.error("Too many inputs for predecoder.", -1)
y_offset = pin.cy()
in_pin = "in_{}".format(num)
a_pin = "A_{}".format(num)
@ -283,10 +284,14 @@ class hierarchical_predecode(design.design):
if self.number_of_inputs == 2:
gate_lst = ["A", "B"]
else:
elif self.number_of_inputs == 3:
gate_lst = ["A", "B", "C"]
elif self.number_of_inputs == 4:
gate_lst = ["A", "B", "C", "D"]
else:
debug.error("Invalid number of nand inputs for decode", -1)
# this will connect pins A,B or A,B,C
# this will connect pins A,B or A,B,C or A,B,C,D
for rail_pin, gate_pin in zip(index_lst, gate_lst):
pin = self.and_inst[k].get_pin(gate_pin)
pin_pos = pin.center()

16
compiler/modules/hierarchical_predecode4x16.py
View File

@ -32,14 +32,14 @@ class hierarchical_predecode4x16(hierarchical_predecode):
["in_0", "inbar_1", "in_2", "inbar_3", "out_5", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "inbar_3", "out_6", "vdd", "gnd"],
["in_0", "in_1", "in_2", "inbar_3", "out_7", "vdd", "gnd"],
["inbar_0", "inbar_1", "inbar_2", "in_3", "out_0", "vdd", "gnd"],
["in_0", "inbar_1", "inbar_2", "in_3", "out_1", "vdd", "gnd"],
["inbar_0", "in_1", "inbar_2", "in_3", "out_2", "vdd", "gnd"],
["in_0", "in_1", "inbar_2", "in_3", "out_3", "vdd", "gnd"],
["inbar_0", "inbar_1", "in_2", "in_3", "out_4", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "in_3", "out_5", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "in_3", "out_6", "vdd", "gnd"],
["in_0", "in_1", "in_2", "in_3", "out_7", "vdd", "gnd"] ]
["inbar_0", "inbar_1", "inbar_2", "in_3", "out_8", "vdd", "gnd"],
["in_0", "inbar_1", "inbar_2", "in_3", "out_9", "vdd", "gnd"],
["inbar_0", "in_1", "inbar_2", "in_3", "out_10", "vdd", "gnd"],
["in_0", "in_1", "inbar_2", "in_3", "out_11", "vdd", "gnd"],
["inbar_0", "inbar_1", "in_2", "in_3", "out_12", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "in_3", "out_13", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "in_3", "out_14", "vdd", "gnd"],
["in_0", "in_1", "in_2", "in_3", "out_15", "vdd", "gnd"] ]
self.create_and_array(connections)

2
compiler/pgates/pand4.py
View File

@ -145,7 +145,7 @@ class pand4(pgate.pgate):
width=pin.width(),
height=pin.height())
for pin_name in ["A", "B", "C"]:
for pin_name in ["A", "B", "C", "D"]:
pin = self.nand_inst.get_pin(pin_name)
self.add_layout_pin_rect_center(text=pin_name,
layer=pin.layer,

5
compiler/tests/06_hierarchical_predecode4x16_test.py
View File

@ -8,14 +8,15 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING hierarchical_predecode4x16_test")
# @unittest.skip("SKIPPING hierarchical_predecode4x16_test")
class hierarchical_predecode4x16_test(openram_test):
def runTest(self):