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Fix replica column bit index

This commit is contained in:
mrg 2020-12-14 14:18:39 -08:00
parent 2954f13294
commit da48b8d98c
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/replica_column.py
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@ -180,7 +180,7 @@ class replica_column(bitcell_base_array):
for port in self.all_ports:
for row in range(row_range_min, row_range_max):
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
self.add_layout_pin(text="wl_{0}_{1}".format(port, row - row_range_min),
layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1),
width=self.width,