luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Col decoders are anything not bitcell pitch.

This commit is contained in:
mrg 2020-06-25 14:25:48 -07:00
parent f84ee04fa9
commit 66df659ad4
2 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/modules/hierarchical_decoder.py
View File

@ -78,10 +78,12 @@ class hierarchical_decoder(design.design):
def add_decoders(self):
""" Create the decoders based on the number of pre-decodes """
self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4")
self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4",
height=self.cell_height)
self.add_mod(self.pre2_4)
self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8")
self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8",
height=self.cell_height)
self.add_mod(self.pre3_8)
def determine_predecodes(self, num_inputs):

11
compiler/modules/hierarchical_predecode.py
View File

@ -24,12 +24,11 @@ class hierarchical_predecode(design.design):
if not height:
self.cell_height = b.height
self.column_decoder = False
elif height != b.height:
self.cell_height = height
self.column_decoder = True
else:
self.cell_height = b.height
self.column_decoder = False
self.cell_height = height
# If we are pitch matched to the bitcell, it's a predecoder
# otherwise it's a column decoder (out of pgates)
self.column_decoder = (height != b.height)
self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
design.design.__init__(self, name)
@ -311,7 +310,7 @@ class hierarchical_predecode(design.design):
""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
# In sky130, we use hand-made decoder cells with vertical power
if not self.column_decoder:
if OPTS.tech_name == "sky130" and not self.column_decoder:
for n in ["vdd", "gnd"]:
# This makes a wire from top to bottom for both inv and and gates
for i in [self.inv_inst, self.and_inst]: