mirror of https://github.com/VLSIDA/OpenRAM.git
Extend pin correct length in new array.
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@ -28,7 +28,7 @@ class sense_amp_array(design.design):
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.columns = word_size * words_per_row
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self.num_cols = word_size * words_per_row
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self.offsets = offsets
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if not num_spare_cols:
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self.num_spare_cols = 0
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@ -121,7 +121,7 @@ class sense_amp_array(design.design):
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for i in range(self.num_cols + self.num_spare_cols):
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self.offsets.append(i * self.bitcell.width)
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for i, xoffset in enumerate(self.offsets[0:self.columns:self.words_per_row]):
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for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]):
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if cell_properties.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
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mirror = "MY"
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xoffset = xoffset + self.amp_spacing
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@ -132,7 +132,7 @@ class sense_amp_array(design.design):
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self.local_insts[i].place(offset=amp_position, mirror=mirror)
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# place spare sense amps (will share the same enable as regular sense amps)
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for i, xoffset in enumerate(self.offsets[self.columns:]):
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for i, xoffset in enumerate(self.offsets[self.num_cols:]):
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index = self.word_size + i
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if cell_properties.bitcell.mirror.y and (index + self.column_offset) % 2:
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mirror = "MY"
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@ -70,7 +70,7 @@ class write_driver_array(design.design):
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self.place_write_array()
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self.width = self.driver_insts[-1].rx()
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self.width_regular_cols = self.driver_insts[-self.num_spare_cols].rx()
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self.width_regular_cols = self.driver_insts[-self.num_spare_cols].lx()
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self.height = self.driver.height
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self.add_layout_pins()
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self.add_boundary()
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@ -252,7 +252,7 @@ class write_driver_array(design.design):
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en_pin = inst.get_pin(inst.mod.en_name)
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self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
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layer="m1",
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offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
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offset=en_pin.lr() + vector(-drc("minwidth_m1"), 0))
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else:
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inst = self.driver_insts[0]
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