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sense_amp/array: Remove hardcoded pin names 

all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2020-02-17 14:25:55 +01:00
parent 9a12b68680
commit 680dc6d2c7
2 changed files with 35 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
compiler/modules/sense_amp.py
View File

@ -35,6 +35,14 @@ class sense_amp(design.design):
def get_br_names(self):
return "br"
@property
def dout_name(self):
return "dout"
@property
def en_name(self):
return "en"
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create sense_amp")
@ -79,11 +87,10 @@ class sense_amp(design.design):
def get_enable_name(self):
"""Returns name used for enable net"""
#FIXME: A better programmatic solution to designate pins
enable_name = "en"
enable_name = self.en_name
debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
return enable_name
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)

44
compiler/modules/sense_amp_array.py
View File

@ -41,6 +41,14 @@ class sense_amp_array(design.design):
br_name = self.amp.get_br_names()
return br_name
@property
def data_name(self):
return "data"
@property
def en_name(self):
return "en"
def create_netlist(self):
self.add_modules()
self.add_pins()
@ -62,10 +70,10 @@ class sense_amp_array(design.design):
def add_pins(self):
for i in range(0,self.word_size):
self.add_pin("data_{0}".format(i), "OUTPUT")
self.add_pin("bl_{0}".format(i), "INPUT")
self.add_pin("br_{0}".format(i), "INPUT")
self.add_pin("en", "INPUT")
self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
self.add_pin(self.en_name, "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
@ -85,10 +93,10 @@ class sense_amp_array(design.design):
name = "sa_d{0}".format(i)
self.local_insts.append(self.add_inst(name=name,
mod=self.amp))
self.connect_inst(["bl_{0}".format(i),
"br_{0}".format(i),
"data_{0}".format(i),
"en", "vdd", "gnd"])
self.connect_inst([self.get_bl_name() + "_{0}".format(i),
self.get_br_name() + "_{0}".format(i),
self.data_name + "_{0}".format(i),
self.en_name, "vdd", "gnd"])
def place_sense_amp_array(self):
from tech import cell_properties
@ -128,22 +136,22 @@ class sense_amp_array(design.design):
start_layer="m2",
vertical=True)
bl_pin = inst.get_pin("bl")
br_pin = inst.get_pin("br")
dout_pin = inst.get_pin("dout")
self.add_layout_pin(text="bl_{0}".format(i),
bl_pin = inst.get_pin(inst.mod.get_bl_names())
br_pin = inst.get_pin(inst.mod.get_br_names())
dout_pin = inst.get_pin(inst.mod.dout_name)
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
layer="m2",
offset=bl_pin.ll(),
width=bl_pin.width(),
height=bl_pin.height())
self.add_layout_pin(text="br_{0}".format(i),
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
layer="m2",
offset=br_pin.ll(),
width=br_pin.width(),
height=br_pin.height())
self.add_layout_pin(text="data_{0}".format(i),
self.add_layout_pin(text=self.data_name + "_{0}".format(i),
layer="m2",
offset=dout_pin.ll(),
width=dout_pin.width(),
@ -152,8 +160,8 @@ class sense_amp_array(design.design):
def route_rails(self):
# add sclk rail across entire array
sclk_offset = self.amp.get_pin("en").ll().scale(0,1)
self.add_layout_pin(text="en",
sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
self.add_layout_pin(text=self.en_name,
layer="m1",
offset=sclk_offset,
width=self.width,