mirror of https://github.com/VLSIDA/OpenRAM.git
Make width based on bitcell offsets, not number of columns
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@ -97,7 +97,7 @@ class write_mask_and_array(design.design):
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for i in range(self.columns):
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self.offsets.append((i + self.write_size - 1) * self.driver_spacing)
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self.width = self.columns * self.bitcell.width
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self.width = self.offsets[-1] + self.bitcell.width
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self.height = self.and2.height
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write_bits = self.columns / self.num_wmasks
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